Electronic circuits and circuit elements

ABSTRACT

A method of manufacturing an electronic circuit comprising a first device and at least a second device is disclosed. The first device comprises a first terminal, a second terminal, and a first body of semiconductive material providing a semiconductive path between the first and second terminals, and the second device comprises a third terminal, a fourth terminal, and a second body of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal. The method comprises: forming the first body; and forming the second body, wherein the first body comprises a first quantity of a metal oxide and the second body comprises a second quantity of said metal oxide. Corresponding electronic circuits are disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 U.S.C. 371 ofPCT Application No. PCT/GB2020/051986, having an international filingdate of 19 Aug. 2020, which designated the United States, which PCTapplication claimed the benefit of Great Britain Application No.1912025.2, filed 21 Aug. 2019 and Great Britain Application No.2000887.6, filed 21 Jan. 2020, each of which are incorporated herein byreference in their entirety.

FIELD

The present invention relates to electronic circuits (and in particular,although not exclusively, to flexible integrated circuits, i.e. flexibleICs), and components (i.e. elements) of such circuits. Certainembodiments are concerned with electronic circuits in which two or moreof the following types of circuit elements are integrated: transistor;resistor; and Schottky diode. Thus, certain embodiments of the presentinvention relate to electronic circuits comprising at least onetransistor and at least one resistor, and in particular, although notexclusively, to flexible integrated circuits comprising at least onetransistor and at least one resistor. Certain embodiments relate toelectronic circuits (e.g. flexible ICs) comprising: at least onetransistor and at least one Schottky diode; at least one resistor and atleast one Schottky diode; and at least one transistor, at least oneSchottky diode, and at least one resistor. Certain embodiments relate todual gate transistors and electronic circuits comprising suchtransistors, for example circuits integrating such transistors with atleast one Schottky diode and/or at least one resistor.

BACKGROUND

Whilst flexible integrated circuits (FlexICs) are known, there remainfew technologies capable of producing low cost FlexICs. Most FlexICtechnologies have been developed for application to displays, ratherthan to digital or analogue processing, sensing and communication. Oneof the most promising FlexIC technologies is based on thin filmtransistors (TFTs) incorporating metal oxide semiconductors. The highoptical transmission of these devices has contributed to theirdevelopment for displays, however the commercially feasible materialsare presently all n-type semiconductors. This means that metaloxide-based FlexIC architectures cannot incorporate silicon-basedcircuit designs of the past three decades, which are almost exclusivelybased on complementary semiconductors (i.e. the circuits contain bothn-type and p-type transistors). These CMOS circuits have enabled adegree of integration, efficiency and complexity that has so far beenunachievable in any commercial unipolar (n-type or p-type) technologies.Certain aspects and embodiments of the present invention are concernedwith the development of metal oxide-based FlexICs to enable low costapplications in processing, sensing, communication and other fields, andhave therefore required a different approach.

In the past, unipolar integrated circuits (ICs) based on silicon havefeatured integrated resistors. However, typically these resistors hadrelatively low resistivity of up to ˜50 k Ω/□ (50 kOhm per square). Thislimited the economically viable (i.e. sufficiently small in ICfootprint) resistor range. In turn, this limitation drove thedevelopment of circuit architectures using diode- or transistor-loadtransistors, which suffered from high power consumption and slowswitching speeds in comparison to contemporary circuits based on bipolartransistors. Furthermore, these resistor technologies were applicableonly to bulk crystalline semiconductors. Later IC processes featuredthin film metal- or polysilicon-based resistors in ‘back end of line’(BEOL) layers above the active devices. These resistors have even lowerresistivity of up to around 100 Ω/□ (100 Ohm per square), however.

Schottky diodes are well-known electronic components, typicallyproviding very fast switching from their conducting to non-conductingstates and hence they are particularly good for rectifying highfrequency signals. Schottky diodes are also well-known for use innumerous other electronic applications and circuit configurations. WO2019/116020A1 (the contents of which are incorporated herein byreference) discloses a variety of Schottky diodes suitable for use inthin and/or flexible electronic circuits, and which may be integrated inembodiments of the present invention. These Schottky diodes typicallycomprise: a first electrode; a second electrode; and a body (e.g. alayer) of semiconductive material connected to the first electrode at(by) a first interface (junction) and connected to the second electrodeat (by) a second interface (junction), wherein the first interfacecomprises a first planar region lying in a first plane and the firstelectrode has a first projection onto the first plane in a firstdirection normal to the first plane, the second interface comprises asecond planar region lying in a second plane and the second electrodehas a second projection onto the first plane in said first direction, atleast a portion of the second projection lies outside the firstprojection, said second planar region is offset (separated, spaced) fromthe first planar region in said first direction, and one of the firstinterface and the second interface provides a Schottky (rectifying)contact. However, certain embodiments of the present invention mayincorporate Schottky diodes of other configurations, for example purelylateral or purely vertical devices, known in the art.

SUMMARY

Aspects and embodiments of the present invention aim to address at leastone of the problems associated with the prior art. Furthermore, certainaspects and embodiments of the present invention address the problems ofhow to integrate resistors and/or transistors and/or Schottky diodes inelectronic circuits, especially, but not exclusively, electroniccircuits which are at least one of: capable of being produced in highvolumes; capable of being produced at low cost; flexible; transparent;and have a small footprint. Certain aspects and embodiments of thepresent invention also aim to provide resistor geometries, technologies,materials, and methods of their manufacture, which are compatible withincorporation or integration with electronic circuits of any one or moreof the above-mentioned types. Furthermore, certain aspects andembodiments of the present invention address the problem of how tomanufacture circuits, especially flexible ICs, incorporating resistors,where the resistors have resistances in the desired ranges for theirintended applications in the circuits, and yet the circuits have smallfootprints. Certain aspects and embodiments of the present inventionalso aim to provide dual gate transistor geometries, technologies,materials, and methods of their manufacture, which are compatible withincorporation or integration with electronic circuits of any one or moreof the above-mentioned types. Furthermore, certain aspects andembodiments of the present invention address the problem of how tomanufacture circuits, especially flexible ICs, incorporating resistors(and optionally transistors and/or Schottky diodes), where the resistorshave resistances in the desired ranges for their intended applicationsin the circuits, and yet the circuits have small footprints.

In accordance with a first aspect of the present invention there isprovided an electronic circuit (or circuit module) (10000) comprising atransistor (1) and a resistor (2),

the transistor comprising a source terminal (11), a drain terminal (12),a gate terminal (13), and a first body (10) of material providing acontrollable semiconductive channel between the source and drainterminals,

the resistor comprising a first resistor terminal (21), a secondresistor terminal (22), and a second body (20) of material providing aresistive current path between the first resistor terminal and thesecond resistor terminal,

wherein said first body (10) of material comprises a metal oxide (e.g.comprises a first quantity of said metal oxide) and said second body(20) of material comprises said metal oxide (e.g. comprises a secondquantity of said metal oxide).

Advantageously, as the semiconductive first body (channel body) 10 andthe resistor body 20 are each formed from the same metal oxide, they maybe formed, for example by deposition, in the same machine, for examplewithout having to remove the circuit structure between forming the firstquantity of metal oxide and the second. They may be formed sequentially,but under different conditions, the conditions being selected/arrangedsuch that the first body is semiconductive and the second body isresistive, or vice versa. Alternatively, the metal oxide material of thefirst and second bodies may be formed at the same time as each other,for example in a single deposition step, with the difference inelectrical properties being achieved by different doping and/or bydifferent subsequent processing. Furthermore, a combination of differentdeposition conditions, different doping, and/or different subsequentprocessing may be used to achieve different electrical properties of thebodies based on the same metal oxide material.

In certain embodiments, the circuit comprises first and second voltage(supply) rails (61, 62), the resistor is a load resistor connected inseries between one of the source and drain terminals (11, 12 and one ofsaid voltage (supply) rails.

In certain embodiments, the second body (20) of material comprises adopant. In certain such embodiments, the first body (10) of materialdoes not comprise said dopant, and this difference contributes at leastin part to the different electrical properties of the two bodies.

In certain alternative embodiments, first body (10) of materialcomprises a dopant in a first range of concentrations, and said secondbody (20) of material comprises said dopant in a second range ofconcentrations. In certain such embodiments the second range is higherthan said first range, and in others the second range is lower than saidfirst range.

In certain embodiments, at least a portion of the second body (20) hasbeen processed (e.g. annealed, laser annealed, thermally annealed,exposed to electromagnetic radiation, doped, implanted, exposed to aflux of ions) to increase (or decrease) its conductivity.

In certain embodiments, each of the first and second bodies (10, 20)comprises a respective layer, film, or sheet of said metal oxide. Incertain such embodiments, each said layer, film, or sheet has athickness in the range 1 to 200 nm (for example in the range 5 to 50nm).

In certain embodiments, each said layer, film, or sheet has the samethickness.

In certain embodiments, each said layer, film, or sheet is flat(planar). In certain such embodiments, the first and second bodies arecoplanar, although in certain alternative embodiments the first bodylies in a first plane and the second body lies in a second plane, thesecond plane being parallel to said first plane.

In certain embodiments, the second body has a sheet resistance value inthe range 25 kOhm/sq to 20 MOhm/sq (e.g. in the range 50 kOhm/sq to 10MOhm/sq). Advantageously, this enables resistors having resistances inthe ranges desired for a wide variety of applications to bemanufactured, whilst having relatively small/compact footprints. Inother words, the areas of resistive material required may be suitablysmall.

In certain embodiments, each of the first and second bodies issubstantially transparent to electromagnetic radiation in the rangevisible to the naked human eye.

In certain embodiments, the circuit (or circuit module) comprises asubstrate (5) arranged to support, directly or indirectly, each of thetransistor (1) and the resistor (2). In certain embodiments thesubstrate is flexible, as indeed may be the circuit itself.

In certain embodiments, the metal oxide is Indium Gallium Zinc Oxide,IGZO.

In certain embodiments the resistor (2) exhibits a resistance betweenits terminals (21, 22) in the range 10 ohm to 10 MOhm (for example 100ohm or 1 kOhm to 1 or 10 MOhm) at room temperature.

In certain embodiments, the circuit further comprises a second resistor(3) comprising first and second terminals (31, 32) and a third body (30)of material providing a resistive current path between said terminals,wherein said third body of material comprises said metal oxide (e.g.comprises a third quantity of said metal oxide). In certain suchembodiments, each of the second and third bodies is flat (planar),wherein the second body lies in a second plane and the third body liesin a third plane, said third plane being parallel to said second plane.

In certain embodiments, the first and second resistors exhibit differentresistances at room temperature. For example, the second body ofmaterial may comprise a dopant in a second range of concentrations, andsaid third body of material may comprise said dopant in a third range ofconcentrations, said second range being different from said third range.Additionally, or alternatively, the third body (30) may have beenprocessed differently from said second body to achieve the differentresistances.

In certain embodiments, the transistor comprises a second gate terminal(132). This second gate terminal (132) may be arranged on an oppositeside of the first body (10) to the first gate terminal (13, 131), andmay be separated from the semiconductive material of the first body (10)by a further layer, or other body, of dielectric material (42).

Another aspect of the present invention provides a method ofmanufacturing an electronic circuit (or circuit module) (10000)comprising a transistor (1) and a resistor (2), the transistorcomprising a source terminal (11), a drain terminal (12), a gateterminal (13), and a first body (10) of material providing acontrollable semiconductive channel between the source and drainterminals, and the resistor comprising a first resistor terminal (21), asecond resistor terminal (22), and a second body (20) of materialproviding a resistive current path between the first resistor terminaland the second resistor terminal, the method comprising: forming thefirst body (10); and forming the second body (20), wherein the firstbody comprises a first quantity (100) of a metal oxide and the secondbody comprises a second quantity (200) of said metal oxide.

In certain embodiments forming the first body comprises forming saidfirst quantity of said metal oxide, and forming the second bodycomprises forming said second quantity of said metal oxide.

In certain embodiments forming said first quantity comprises formingsaid first quantity (100) directly or indirectly on a first region (51)of a substrate, and forming said second quantity comprises forming saidsecond quantity (200) directly or indirectly on a second region (52) ofthe substrate.

In certain embodiments, said forming of said first quantity comprisesforming said first quantity (100) using a technique selected from a listcomprising: physical deposition; physical vapour deposition (PVD);chemical deposition; chemical vapour deposition (CVD); atomic layerdeposition (ALD); physical-chemical deposition; evaporation; sputtering;sol-gel techniques; chemical bath deposition; spray pyrolysis; platingtechniques; pulsed laser deposition (PLD); solution processing; and spincoating.

In certain embodiments, said forming of said second quantity comprisesforming said second quantity (200) using a technique selected from alist comprising: physical deposition; physical vapour deposition (PVD);chemical deposition; chemical vapour deposition (CVD); atomic layerdeposition (ALD); physical-chemical deposition; evaporation; sputtering;sol-gel techniques; chemical bath deposition; spray pyrolysis; platingtechniques; pulsed laser deposition (PLD); solution processing; and spincoating.

In certain embodiments, forming said first quantity comprises depositingsaid first quantity of said metal oxide.

In certain embodiments forming said second quantity comprises depositingsaid second quantity of said metal oxide.

In certain embodiments, said forming of said first quantity is performedbefore said forming of said second quantity.

In certain embodiments, said forming of said first quantity is performedafter said forming of said second quantity.

In certain embodiments, said forming of said first quantity comprisesforming (e.g. by depositing or otherwise forming) a first layer, film,or sheet (1001) of said metal oxide, said first layer, film, or sheetcomprising said first quantity (100).

In certain embodiments, forming the first body (10) comprises patterningthe first layer, film, or sheet (1001).

In certain embodiments, forming of said second quantity comprisesforming (e.g. by depositing or otherwise forming) a second layer, film,or sheet (2001) of said metal oxide, said second layer, film, or sheetcomprising said second quantity (200).

In certain embodiments, forming the second body (2) comprises patterningthe second layer, film, or sheet (2001).

In certain embodiments, said forming of said first quantity (100) isperformed at the same time as forming said second quantity (200).

In certain embodiments, said forming of said first quantity at the sametime as forming said second quantity comprises forming (e.g. bydepositing or otherwise forming) a layer, film, or sheet (1200) of saidmetal oxide, said layer, film, or sheet (1200) comprising said first andsecond quantities (100, 200).

In certain embodiments, forming the first and second bodies (10, 20)comprises patterning said sheet (1200).

In certain embodiments, the method further comprises doping said firstbody (10) of material with a first dopant to decrease (or increase) anelectrical conductivity of said first body.

In certain embodiments, doping said first body of material comprisesforming said first quantity (100) on a source (71) of said first dopant.

In certain embodiments, the method comprises providing said source (71)of said first dopant directly or indirectly on said first region (51) ofthe substrate.

In certain embodiments, doping said first body of material comprisesforming a source of said first dopant on said first body of material.

In certain embodiments, the method further comprises doping said secondbody (20) of material with a second dopant to increase (or decrease) anelectrical conductivity of said second body.

In certain embodiments, doping said second body of material comprisesforming said second quantity (200) on a source (72) of said seconddopant.

In certain embodiments, the method further comprises providing saidsource (72) of said second dopant directly or indirectly on said secondregion (52) of the substrate.

In certain embodiments, doping said second body of material comprisesforming a source of said second dopant on said second body of material.

In certain embodiments, the method further comprises processing saidsecond quantity (200) of said metal oxide to increase or decrease anelectrical conductivity of the second body.

In certain embodiments, processing said second quantity comprisesannealing (or otherwise processing) at least a portion of said secondquantity to increase or decrease its conductivity.

In certain embodiments, said processing of the second body (e.g. byannealing, or other means) comprises exposing said at least a portion toelectromagnetic radiation.

In certain embodiments, the method further comprises providing saidelectromagnetic radiation from a lamp. In certain other embodiments, theelectromagnetic radiation may be provided from a laser.

In certain embodiments, the method further comprises shielding at leasta portion of the first quantity (100) of said metal oxide from saidelectromagnetic radiation.

In certain embodiments, said shielding comprises using said gateterminal (13) to shield said at least a portion of the first quantity(100) from said electromagnetic radiation.

In certain embodiments, each of the first and second bodies (10, 20)comprises a respective layer, film, or sheet of said metal oxide, andeach said respective layer, film, or sheet may have a thickness in therange 1 to 200 nm (for example 5 to 50 nm).

In certain embodiments, each said respective layer, film, or sheet hasthe same thickness. In certain embodiments, each said respective layer,film, or sheet is flat (planar).

In certain embodiments, the method comprises forming the first andsecond bodies (10, 20) in a common plane.

In certain embodiments, the method comprises forming the first body in afirst plane and forming the second body in a second plane, said secondplane being parallel to said first plane.

In certain embodiments, the second body has a sheet resistance value inthe range 25 kOhm/sq to 20 MOhm/sq (e.g. in the range 50 kOhm/sq to 10MOhm/sq).

In certain embodiments, each of the first and second bodies issubstantially transparent to electromagnetic radiation in the rangevisible to the naked human eye.

In certain embodiments, the method further comprises providing asubstrate (5) arranged to support, directly or indirectly, each of thetransistor and the resistor, and said forming of the first and secondbodies comprises forming the first body (10) on or over a first region(51) of the substrate and forming the second body (20) on or over asecond region (52) of the substrate.

In certain embodiments, said substrate (5) is flexible.

In certain embodiments, the method further comprises forming the sourceterminal, drain terminal, first resistor terminal, and second resistorterminal after forming the first and second bodies. In certainalternative embodiments, the method further comprises forming the sourceterminal, drain terminal, first resistor terminal, and second resistorterminal before forming the first and second bodies, for example to formbottom contact devices.

In certain embodiments, said metal oxide is Indium Gallium Zinc Oxide,IGZO.

In certain embodiments, said resistor exhibits a resistance between itsterminals in the range 10 ohm to 10 MOhm (for example 100 ohm or 1 kOhmto 1 or 10 MOhm) at room temperature.

In certain embodiments, the circuit further comprises a second resistor(3) having first and second terminals (31, 32) and a third body (30) ofmaterial providing a resistive current path between said terminals, themethod comprising forming said third body (30) of material, said thirdbody comprising a third quantity (300) of said metal oxide. The secondresistor may, for example, be in a different layer of the circuit fromthe first resistor.

In certain embodiments, the method further comprises doping orprocessing said third body differently from said second body, such thatthe first and second resistors exhibit different resistances at roomtemperature. For example, one of the resistor bodies may be shieldedfrom exposure to irradiation (e.g. UV irradiation), whilst the other isunshielded and hence receives UV irradiation and as a result has itsconductivity increased or decreased.

In certain embodiments, said resistor is a load resistor connected inseries between one of the source and drain terminals and a voltage(supply) rail.

In certain embodiments, the electronic circuit is flexible.

Another aspect of the present invention provides a resistor comprising afirst resistor terminal (21), a second resistor terminal (22), and abody (20) of material providing a resistive current path between thefirst resistor terminal and the second resistor terminal, wherein thebody (20) covers at least part of an upper surface of the first resistorterminal (21), and the second resistor terminal (22) covers at least aportion of a top surface of the second body (20). In other words, thebody (20) may at least partially overlap the first resistor terminal(21), and the second resistor terminal (22) may at least partiallyoverlap the second body. The resistor may be formed on a substrate, orsome other supporting body or structure, and the body (20) may comprisea quantity of a metal oxide material.

Another aspect of the present invention provides a method ofmanufacturing a resistor comprising a first resistor terminal (21), asecond resistor terminal (22), and a body (20) of material providing aresistive current path between the first resistor terminal and thesecond resistor terminal, the method comprising: forming the body, thenforming the first resistor terminal, and then forming the secondresistor terminal. In an alternative aspect, the method comprises:forming the first resistor terminal (21), then forming the body (20),and then forming the second resistor terminal (22). In a further aspect,the method comprises: forming the first resistor terminal (21), thenforming the second resistor terminal (22), and then forming the body(20). Thus, the resistor terminals are not formed at the same time (orin the same processing step or sequence of steps) as each other.

Further aspects of the invention provide a resistor as defined inconnection with any one of the above-mentioned aspects or embodiments,and a method of manufacturing such a resistor.

Another aspect of the present invention provides an electronic circuit(or circuit module) (10000) comprising a Schottky diode (3000) and aresistor (2),

the Schottky diode comprising a first electrode (3001), a secondelectrode (3002), and a first body (3010) (e.g. a layer) ofsemiconductive material connected to the first electrode at (by) a firstinterface (junction) and connected to the second electrode at (by) asecond interface (junction),

the resistor comprising a first resistor terminal (21), a secondresistor terminal (22), and a second body (20) of material providing aresistive current path between the first resistor terminal and thesecond resistor terminal,

wherein said first body (3010) of semiconductive material comprises ametal oxide (e.g. comprises a first quantity of said metal oxide) andsaid second body (20) of material comprises said metal oxide (e.g.comprises a second quantity of said metal oxide).

Advantageously, as the semiconductive first body (Schottky diode body)3010 and the resistor body 20 are each formed from the same metal oxide,they may be formed, for example by deposition, in the same machine, forexample without having to remove the circuit structure between formingthe first quantity of metal oxide and the second. They may be formedsequentially, but under different conditions, the conditions beingselected/arranged such that the first body is semiconductive and thesecond body is resistive. Alternatively, the metal oxide material of thefirst and second bodies may be formed at the same time as each other,for example in a single deposition step, with the difference inelectrical properties being achieved by different doping and/or bydifferent subsequent processing. Furthermore, a combination of differentdeposition conditions, different doping, and/or different subsequentprocessing may be used to achieve different electrical properties of thebodies based on the same metal oxide material.

Features of any of the above-mentioned aspects and embodiments of theinvention may be incorporated in embodiments of this further aspect(incorporating at least one Schottky diode and at least one resistor)with corresponding advantage.

For example, in certain embodiments, the second body (20) of materialcomprises a dopant. In certain such embodiments, the first body (3010)of semiconductive material does not comprise said dopant, and thisdifference contributes at least in part to the different electricalproperties of the two bodies.

In certain alternative embodiments, first body (3010) of semiconductivematerial comprises a dopant in a first range of concentrations, and saidsecond body (20) of material comprises said dopant in a second range ofconcentrations. In certain such embodiments the second range is higherthan said first range, and in others the second range is lower than saidfirst range.

In certain embodiments, each of the first and second bodies (3010, 20)comprises a respective layer, film, or sheet of said metal oxide. Incertain such embodiments, each said layer, film, or sheet has athickness in the range 1 to 200nm (for example in the range 5 to 50 nm).

In certain embodiments, the circuit (or circuit module) comprises asubstrate (5) (which may also be referred to as a supporting layer,underlayer, or structure) arranged to support, directly or indirectly,each of the Schottky diode (3000) and the resistor (2). In certainembodiments the substrate is flexible, as indeed may be the circuititself.

A further aspect of the present invention provides a method ofmanufacturing an electronic circuit (or circuit module)(10000)comprising a Schottky diode (3000) and a resistor (2), the Schottkydiode comprising a first electrode (3001), a second electrode (3002),and a first body (3010) (e.g. a layer) of semiconductive materialconnected to the first electrode at (by) a first interface (junction)and connected to the second electrode at (by) a second interface(junction), the resistor comprising a first resistor terminal (21), asecond resistor terminal (22), and a second body (20) of materialproviding a resistive current path between the first resistor terminaland the second resistor terminal, the method comprising: forming thefirst body (3010); and forming the second body (20), wherein the firstbody comprises a first quantity (3100) of a metal oxide and the secondbody comprises a second quantity (200) of said metal oxide.

Again, features of any of the above-mentioned aspects and embodiments ofthe invention may be incorporated in embodiments of this further aspectwith corresponding advantage.

For example, in certain embodiments forming the first body comprisesforming said first quantity (3100) of said metal oxide, and forming thesecond body comprises forming said second quantity (200) of said metaloxide.

In certain embodiments forming said first quantity comprises formingsaid first quantity (3100) directly or indirectly on a first region (51)of a substrate, and forming said second quantity comprises forming saidsecond quantity (200) directly or indirectly on a second region (52) ofthe substrate.

In certain embodiments, said forming of said first quantity (3100)comprises forming said first quantity (3100) using a technique selectedfrom a list comprising: physical deposition; physical vapour deposition(PVD); chemical deposition; chemical vapour deposition (CVD); atomiclayer deposition (ALD); physical-chemical deposition; evaporation;sputtering; sol-gel techniques; chemical bath deposition; spraypyrolysis; plating techniques; pulsed laser deposition (PLD); solutionprocessing; and spin coating.

In certain embodiments, said forming of said first quantity (3100) isperformed before said forming of said second quantity (200).

In certain embodiments, said forming of said first quantity (3100) isperformed after said forming of said second quantity (200).

In certain embodiments, said forming of said first quantity (3100)comprises forming (e.g. by depositing or otherwise forming) a layer,film, or sheet (1001) of said metal oxide, said layer, film, or sheetcomprising said first quantity (3100).

In certain embodiments, forming the first body (3010) comprisespatterning the layer, film, or sheet.

In certain embodiments, said forming of said first quantity (3100) isperformed at the same time as forming said second quantity (200).

In certain embodiments, said forming of said first quantity (3100) atthe same time as forming said second quantity comprises forming (e.g. bydepositing or otherwise forming) a layer, film, or sheet of said metaloxide, said layer, film, or sheet comprising said first and secondquantities (3100, 200). In certain embodiments, forming the first andsecond bodies (3010, 20) comprises patterning that sheet.

In certain embodiments, the method further comprises doping said firstbody (3010) of material with a first dopant to decrease (or increase) anelectrical conductivity of said first body.

In certain embodiments, doping said first body of material comprisesforming said first quantity (3100) on a source (71) of said firstdopant.

In certain embodiments, the method comprises providing said source (71)of said first dopant directly or indirectly on said first region (51) ofthe substrate.

In certain embodiments, doping said first body of material comprisesforming a source of said first dopant on said first body of material.

In certain embodiments, the method further comprises doping said secondbody (20) of material with a second dopant to increase (or decrease) anelectrical conductivity of said second body.

In certain embodiments, doping said second body of material comprisesforming said second quantity (200) on a source (72) of said seconddopant.

In certain embodiments, the method further comprises providing saidsource (72) of said second dopant directly or indirectly on said secondregion (52) of the substrate.

In certain embodiments, doping said second body of material comprisesforming a source of said second dopant on said second body of material.

In certain embodiments, the method further comprises processing saidsecond quantity (200) of said metal oxide to increase or decrease anelectrical conductivity of the second body.

In certain embodiments, processing said second quantity comprisesannealing at least a portion of said second quantity to increase ordecrease its conductivity.

In certain embodiments, said annealing comprises exposing said at leasta portion to electromagnetic radiation.

In certain embodiments, the method further comprises providing saidelectromagnetic radiation from a lamp.

In certain embodiments, the method further comprises shielding at leasta portion of the first quantity (3100) of said metal oxide from saidelectromagnetic radiation.

In certain embodiments, each of the first and second bodies (3010, 20)is substantially transparent to electromagnetic radiation in the rangevisible to the naked human eye.

In certain embodiments, the method further comprises providing asubstrate (5) (which may also be referred to as a supporting layer,underlayer, or structure) arranged to support, directly or indirectly,each of the Schottky diode and the resistor, and said forming of thefirst and second bodies comprises forming the first body (3010) on orover a first region (51) of the substrate and forming the second body(20) on or over a second region (52) of the substrate.

In certain embodiments, the method further comprises forming the firstelectrode, second electrode, first resistor terminal, and secondresistor terminal after forming the first and second bodies (3010, 20).In certain alternative embodiments, the method further comprises formingthe first electrode, second electrode, first resistor terminal, andsecond resistor terminal before forming the first and second bodies, forexample to form bottom contact devices.

In certain embodiments, the circuit further comprises a second resistor(3) having first and second terminals (31, 32) and a third body (30) ofmaterial providing a resistive current path between said terminals, themethod comprising forming said third body (30) of material, said thirdbody comprising a third quantity (300) of said metal oxide. The secondresistor may, for example, be in a different layer of the circuit fromthe first resistor.

In certain embodiments, the method further comprises doping orprocessing said third body differently from said second body, such thatthe first and second resistors exhibit different resistances at roomtemperature. For example, one of the resistor bodies may be shieldedfrom exposure to irradiation (e.g. UV irradiation), whilst the other isunshielded and hence receives UV irradiation and as a result has itsconductivity increased or decreased.

A further aspect of the invention provides an electronic circuit (orcircuit module) (10000) comprising a transistor (1) and a Schottky diode(3000),

the transistor comprising a source terminal (11), a drain terminal (12),a gate terminal (13), and a first body (10) of material providing acontrollable semiconductive channel between the source and drainterminals,

the Schottky diode comprising a first electrode (3001), a secondelectrode (3002), and a second body (3010) (e.g. a layer) ofsemiconductive material connected to the first electrode at (by) a firstinterface (junction) and connected to the second electrode at (by) asecond interface (junction), wherein said first body (10) of materialcomprises a metal oxide (e.g. comprises a first quantity of said metaloxide) and said second body (3010) of material comprises said metaloxide (e.g. comprises a second quantity of said metal oxide).

Advantageously, as the semiconductive first body (channel body) 10 andthe Schottky body 3010 are each formed from the same metal oxide, theymay be formed, for example by deposition, in the same machine, forexample without having to remove the circuit structure between formingthe first quantity of metal oxide and the second. They may be formedsequentially (under the same or different conditions, the conditionsbeing selected/arranged to produce semiconductive paths having thedesired characteristics). Alternatively, they may be formed at the sametime as each other, for example in a single deposition step. Ifdifferent semiconductive properties are required for the transistorchannel and Schottky body, then the difference in electrical propertiesmay be achieved by different doping and/or by different subsequentprocessing. Furthermore, a combination of different depositionconditions, different doping, and/or different subsequent processing maybe used to achieve different electrical properties of the bodies basedon the same metal oxide material.

In certain embodiments, the circuit comprises first and second voltage(supply) rails (61, 62), the Schottky diode is a load connected inseries between one of the source and drain terminals (11, 12 and one ofsaid voltage (supply) rails.

Again, features of any of the above-mentioned aspects and embodiments ofthe invention may be incorporated in embodiments of this further aspect(comprising at least one transistor and at least one Schottky diode)with corresponding advantage.

For example, in certain embodiments, the second body (3010) of materialcomprises a dopant. In certain such embodiments, the first body (10) ofmaterial does not comprise said dopant, and this difference contributesat least in part to the different electrical properties of the twobodies.

In certain alternative embodiments, first body (10) of materialcomprises a dopant in a first range of concentrations, and said secondbody (3010) of material comprises said dopant in a second range ofconcentrations. In certain such embodiments the second range is higherthan said first range, and in others the second range is lower than saidfirst range.

In certain embodiments, at least a portion of the second body (3010) hasbeen processed (e.g. annealed, laser annealed, thermally annealed,exposed to electromagnetic radiation, doped, implanted, exposed to aflux of ions) to increase or decrease its conductivity.

In certain embodiments, each of the first and second bodies (10, 3010)comprises a respective layer, film, or sheet of said metal oxide.

In certain embodiments, the circuit (or circuit module) comprises asubstrate (5) arranged to support, directly or indirectly, each of thetransistor (1) and the Schottky diode (3000). In certain embodiments thesubstrate is flexible, as indeed may be the circuit itself.

In certain embodiments, the circuit further comprises at least oneresistor (2) comprising first and second terminals (21, 22) and aresistor body (20) of material providing a resistive current pathbetween said terminals (21, 22), wherein said resistor body of materialcomprises said metal oxide (e.g. comprises a third quantity of saidmetal oxide).

In certain embodiments, the circuit comprises at least two suchresistors, which may be arranged to exhibit different resistances atroom temperature, this difference being achieved using any of thetechniques described above.

In certain embodiments, the transistor comprises a second gate terminal(132). This second gate terminal (132) may be arranged on an oppositeside of the first body (10) to the first gate terminal (13, 131), andmay be separated from the semiconductive material of the first body (10)by a further layer, or other body, of dielectric material (42).

A further aspect of the present invention provides a method ofmanufacturing an electronic circuit (or circuit module)(10000)comprising a transistor (1) and a Schottky diode, the transistorcomprising a source terminal (11), a drain terminal (12), a gateterminal (13), and a first body (10) of material providing acontrollable semiconductive channel between the source and drainterminals, and the Schottky diode comprising a first electrode (3001), asecond electrode (3002), and a second body (3010) (e.g. a layer) ofsemiconductive material connected to the first electrode at (by) a firstinterface (junction) and connected to the second electrode at (by) asecond interface (junction), the method comprising: forming the firstbody (10); and forming the second body (30210), wherein the first bodycomprises a first quantity (100) of a metal oxide and the second bodycomprises a second quantity (3100) of said metal oxide.

Again, features of any of the above-mentioned aspects and embodiments ofthe invention may be incorporated in embodiments of this further aspectwith corresponding advantage.

For example, in certain embodiments forming the first body comprisesforming said first quantity (100) of said metal oxide, and forming thesecond body (3010) comprises forming said second quantity (3100) of saidmetal oxide.

In certain embodiments forming said first quantity comprises formingsaid first quantity (100) directly or indirectly on a first region (51)of a substrate, and forming said second quantity comprises forming saidsecond quantity (3100) directly or indirectly on a second region (52) ofthe substrate.

In certain embodiments, said forming of said first quantity (100)comprises forming said first quantity (100) using a technique selectedfrom a list comprising: physical deposition; physical vapour deposition(PVD); chemical deposition; chemical vapour deposition (CVD); atomiclayer deposition (ALD); physical-chemical deposition; evaporation;sputtering; sol-gel techniques; chemical bath deposition; spraypyrolysis; plating techniques; pulsed laser deposition (PLD); solutionprocessing; and spin coating.

In certain embodiments, said forming of said second quantity (3100)comprises forming said second quantity (200) using a technique selectedfrom a list comprising: physical deposition; physical vapour deposition(PVD); chemical deposition; chemical vapour deposition (CVD); atomiclayer deposition (ALD); physical-chemical deposition; evaporation;sputtering; sol-gel techniques; chemical bath deposition; spraypyrolysis; plating techniques; pulsed laser deposition (PLD); solutionprocessing; and spin coating.

In certain embodiments, said forming of said first quantity (100) isperformed before said forming of said second quantity (3100).

In certain embodiments, said forming of said first quantity (100) isperformed after said forming of said second quantity (3100).

In certain embodiments, said forming of said first quantity (100) isperformed at the same time as forming said second quantity (3100).

In certain embodiments, said forming of said first quantity at the sametime as forming said second quantity comprises forming (e.g. bydepositing or otherwise forming) a layer, film, or sheet of said metaloxide comprising said first and second quantities (100, 3100).

In certain embodiments, the method comprises forming a second gateterminal on an opposite side of the first body (10) to the first gateterminal (13, 131),

In certain embodiments, the method further comprises providing asubstrate (5) arranged to support, directly or indirectly, each of thetransistor and the Schottky diode (3000).

Another aspect of the invention provides a transistor (1) comprising: asource terminal (11), a drain terminal (12), a first body (10) ofmaterial providing a controllable semiconductive channel between thesource and drain terminals, a first gate terminal (131) arranged on oneside of (e.g. under) the first body (10), and a second gate terminal(132) arranged on an opposite side (e.g. above) the first body (10).

Again, features of any of the above-mentioned aspects and embodiments ofthe invention may be incorporated in embodiments of this further aspectwith corresponding advantage.

In certain embodiments, the first gate terminal (131), first body (10),and the second gate terminal (132) are arranged as a stack in a first(i.e. nominally vertical) direction, with the first body (10) beingarranged above the first gate terminal (131) and separated from thefirst gate terminal (in said first direction) by a first layer or bodyof dielectric material (41), the second gate terminal (132) beingarranged above the first body (10) and separated from the first body(10) (in said first direction) by a second layer or body of dielectricmaterial (42), and the source and drain terminals being arranged suchthat there is no overlap between projections of either gate terminalwith projections of either the source or drain terminals onto a planenormal to said first direction (i.e. a horizontal plane, normal to thevertical direction.

In certain embodiments, the first and second gate terminals are alignedand arranged to have the same projections as each other onto said plane.In certain embodiments, edges of the source and drain terminals arearranged to coincide with edges of the aligned gate terminals.

In certain embodiments, the first body (10) is provided by a firstportion of a layer of metal oxide material, said first portion beingarranged over said first gate terminal, and said source and drainterminals (11, 12) are provided by respective portions of said layer ofmetal oxide material extending beyond edges of the first gate terminal.In certain embodiments, said respective portions have higher electricalconductivity than said first body.

In certain alternative embodiments, said source and drain terminals areeach formed from a metal.

Another aspect of the present invention provides an integrated circuitcomprising a dual gate transistor in accordance with the precedingaspect, and at least one resistor and/or at least one Schottky diode(for example as described above).

A further aspect of the invention provides a method of manufacturing adual-gate transistor, the method comprising: providing a lower gateterminal supported on a substrate; and using the lower gate terminal asa mask in the formation of an upper gate terminal aligned to the lowergate terminal.

In certain embodiments, the method further comprises: using the lowergate terminal as a mask in the formation of source and drain terminalsaligned to the lower gate terminal.

In certain alternative embodiments, the method further comprises: usingthe upper gate terminal as a mask in the formation of source and drainterminals aligned to the lower gate terminal.

A further aspect of the present invention provides: an electroniccircuit (or circuit module) (10000) comprising a first device (1, 3000)and a second device (2, 3000),

the first device comprising a first terminal (11, 3001), a secondterminal (12, 3002), and a first body (10, 3010) of semiconductivematerial providing a semiconductive path between the first and secondterminals,

the second device (2, 3000) comprising a third terminal (21, 3001), afourth terminal (22, 3002), and a second body (20, 3010)) of materialproviding a resistive or semiconductive current path between the thirdterminal and the fourth terminal,

wherein said first body (10, 3010) of material comprises a metal oxide(e.g. comprises a first quantity (100, 3100) of said metal oxide) andsaid second body (20, 3010) of material comprises said metal oxide (e.g.comprises a second quantity (200, 3100) of said metal oxide).

Advantageously, as the first body 10, 3010 and the second body 20, 3010are each formed from the same metal oxide, they may be formed, forexample by deposition, in the same machine, for example without havingto remove the circuit structure between forming the first quantity ofmetal oxide and the second. They may be formed sequentially, under thesame or different conditions, the conditions being selected/arrangedsuch that the first body is semiconductive and the second body issemiconductive or resistive. Alternatively, the metal oxide material ofthe first and second bodies may be formed at the same time as eachother, for example in a single deposition step, with a difference inelectrical properties (if desired) being achieved by different dopingand/or by different subsequent processing. Furthermore, a combination ofdifferent deposition conditions, different doping, and/or differentsubsequent processing may be used to achieve different electricalproperties of the bodies based on the same metal oxide material.

The first device may, for example, be a transistor (e.g. bottom gate,top gate, or dual gate) or a Schottky diode. The second device may, forexample, be a resistor or a Schottky diode. The circuit may furthercomprise at least one further device (e.g. a third device), having abody also formed from the same metal oxide material. That further devicemay, for example, be a transistor, resistor, or Schottky diode. Again,features of any of the above-mentioned aspects and embodiments of theinvention may be incorporated in embodiments of this further aspect withcorresponding advantage.

A further aspect of the present invention provides a method ofmanufacturing an electronic circuit (or circuit module)(10000)comprising a first device (1, 3000) and a second device (2, 3000), thefirst device comprising a first terminal (11, 3001), a second terminal(12, 3002), and a first body (10, 3010) of semiconductive materialproviding a semiconductive path between the first and second terminals,the second device (2, 3000) comprising a third terminal (21, 3001), afourth terminal (22, 3002), and a second body (20, 3010)) of materialproviding a resistive or semiconductive current path between the thirdterminal and the fourth terminal, the method comprising: forming thefirst body (10, 3010); and forming the second body (20, 3010), whereinthe first body comprises a first quantity (100, 3100) of a metal oxideand the second body comprises a second quantity (200, 3100) of saidmetal oxide.

Again, features of any of the above-mentioned aspects and embodiments ofthe invention may be incorporated in embodiments of this further aspectwith corresponding advantage.

In certain embodiments of any aspect of the present invention, at leastone of the quantities of metal oxide may be formed so as to be initiallysemi-conductive material, in a “normally off” condition (e.g.enhancement mode, n-type or p-type). For such materials, since theirconductivities are initially very low (because they are in the normallyoff state), processing arranged to increase their conductivities may beemployed in order to change their electrical characteristics toresistive.

In certain embodiments of any aspect of the present invention, at leastone of the quantities of metal oxide may be formed so as to be initiallysemi-conductive material, in a “normally on” condition (e.g. depletionmode, n-type or p-type). For such materials, since their conductivitiesare initially relatively high (because they are in the normally onstate), processing arranged to decrease their conductivities may beemployed in order to change their electrical characteristics toresistive.

In certain embodiments, exposure to electromagnetic (e.g. optical)radiation may be employed to increase the conductivity of at least partof at least one of the quantities of metal oxide. For example, “normallyoff” semiconductive material (e.g. SnO with a negative thresholdvoltage) may be exposed to radiation to change its characteristics tobeing substantially resistive. NiO can be tuned from p-type to n-typewith an increase in conductivity.

In certain embodiments, exposure to electromagnetic (e.g. optical)radiation may be employed to decrease (reduce) the conductivity of atleast part of at least one of the quantities of metal oxide. Forexample, one may change from n-type material (e.g. SnO2) to p-typematerial (e.g. SnO) using H2 annealing to reduce the Sn(IV). Exposure tooptical radiation may be used on a semiconductor that is “normally on”,e.g. for devices that are p-type with a positive threshold voltage. Thatsemiconductor will have a relative high conductivity initially, and theradiation may be arranged to reduce that conductivity, making thematerial substantially resistive (thus providing a route to integratingresistors in a p-type process in certain embodiments. This reduction inconductivity (to produce a resistor) may also be achieved by reducingthe number of holes, e.g. with hydrogen.

In certain embodiments, exposure to electromagnetic radiation (opticalexcitation) may generate carriers (typically to increase conductivityrather than reduce it). Beside optical excitation, and for example witha dielectric layer present, laser ablation of a semi-conductive film (orother body comprising a quantity of metal oxide material) may bepossible to reduce thickness of the semi-conductive material andtherefore reduce its conductivity.

Other than optical processes, in certain embodiments, opening a windowin a dielectric layer covering a semi-conductive body (e.g. layer)allows introduction of extrinsic dopants and/or modification to themetal oxide material by various means, to change its conductivity. Incertain embodiments, without opening a window, the dielectric layeritself can be engineered (e.g. by reducing thickness, arranging/alteringcomposition, etc.) to promote species diffusion to an underlying oroverlying body of semi-conductive material to reduce (or increase) theconductivity of that body.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects and embodiments of the present invention will now be describedwith reference to the accompanying drawings, of which;

FIG. 1 is a schematic cross-section of part of an electronic circuitembodying the invention;

FIG. 2 is a diagram of an inverter circuit embodying the invention;

FIG. 3 is a diagram of another inverter circuit embodying the presentinvention;

FIGS. 4 and 5 are schematic cross-sections of parts of two otherelectronic circuits embodying the invention;

FIG. 6 illustrates a step in the manufacture of another electroniccircuit embodying the invention;

FIGS. 7A-7B and 8A-8B illustrate steps in two other methods embodyingthe invention;

FIG. 9 is a schematic cross-section of part of another electroniccircuit embodying the present invention, incorporating a transistor andtwo resistors;

FIG. 10 illustrates a step in the manufacture of another electroniccircuit embodying the invention;

FIG. 11 is a schematic cross-section of another embodiment of theinvention;

FIGS. 12A-12H illustrate steps in the method of manufacturing anotherelectronic circuit embodying the invention;

FIGS. 13A-13C, 14A-14B, and 15A-15F illustrate steps in three othermethods embodying the invention;

FIGS. 16-23 illustrate parts of other electronic circuits embodying theinvention;

FIGS. 24A-24H illustrate steps in another method of manufacturing anelectronic circuit in accordance with the present invention;

FIG. 25 is a schematic cross-section of another electronic circuitmodule embodying the invention;

FIGS. 26A-26F illustrate steps in another method embodying theinvention;

FIG. 27 is a schematic cross-section of another electronic circuitmodule embodying the invention and incorporating a resistor an a bottomgate transistor;

FIGS. 28A-28C illustrate steps in another method embodying theinvention;

FIG. 29 is a schematic cross-section of another electronic circuitmodule embodying the invention and incorporating a resistor, bottom gatetransistor, and Schottky diode;

FIGS. 30A-30E illustrate steps in another method embodying theinvention;

FIG. 31 is a schematic cross-section of another electronic circuitmodule embodying the invention and incorporating a resistor, dual-gatetransistor, and Schottky diode;

FIG. 32 is a schematic cross-section of another electronic circuitmodule embodying the invention and incorporating n-type and p-typetransistors, and a Schottky diode;

FIG. 33 illustrates a diode OR gate embodying an aspect of theinvention, and incorporating Schottky diodes and a resistor;

FIG. 34 illustrates a diode AND gate embodying an aspect of theinvention, and incorporating Schottky diodes and a resistor;

FIG. 35 illustrates a diode load inverter embodying an aspect of theinvention, and incorporating a Schottky diode and a transistor;

FIG. 36 illustrates a CMOS inverter circuit module embodying an aspectof the invention, and incorporating an n-channel transistor and ap-channel transistor;

FIG. 37 is a schematic cross section of a dual-gate transistor embodyingthe invention, and suitable for incorporation/integration in circuitsand circuit modules embodying the invention;

FIG. 38 is a schematic cross section of another dual-gate transistorembodying the invention, and suitable for incorporation/integration incircuits and circuit modules embodying the invention;

FIGS. 39A-39F, 40A-40D, 41A-41C, 42A-42E, and 43A-43C illustrate avariety of methods embodying the invention, for manufacturingself-aligned dual-gate transistors;

FIG. 44 illustrates another dual-gate transistor embodying theinvention, and suitable for incorporation/integration in circuits andcircuit modules embodying the invention;

FIG. 45 illustrates another circuit module embodying the invention andincorporating a dual gate transistor and a resistor; and

FIG. 46 illustrates another circuit module embodying the invention.

DETAILED DESCRIPTION

Referring now to FIG. 1, this illustrates part of an electronic circuitembodying the present invention. Typically, of course, the electroniccircuit will comprise numerous other components, and theinterconnections between those components. However, for clarity andsimplicity the figure only illustrates one transistor (1) and oneresistor (2) of the circuit (which may also be referred to as a circuitmodule). The transistor (1) is a field effect transistor, FET,comprising a source terminal (11), a drain terminal (12), a gateterminal (13), and a first body (10) of material providing acontrollable semi-conductive channel between the source and drainterminals. As will be well appreciated, the conductivity of the channelis controlled by application of suitable voltages to the gate terminal(13). The resistor (2) comprises a first resistor terminal (21), asecond resistor terminal (22), and a second body (20) of materialproviding a resistive current path between the first resistor terminaland the second resistor terminal. Although the source and drainterminals (11, 12) and resistor terminals (21, 22) are shown in the ‘topcontact’ architecture in this embodiment, i.e. partly overlying the endportions of the first body (10) and second body (20), other embodimentsof the invention include circuits employing alternative terminalarchitectures. Furthermore, although the FET shown is of the ‘top gate’architecture, with the gate terminal (13) positioned above the firstbody (10), other embodiments of the invention include circuits employingalternative FET architectures. The first body (10) of material comprisesa first quantity of a metal oxide, and the second body (20) comprises asecond quantity of the same metal oxide. Thus, unlike circuits knownfrom the prior art, the circuit comprises a semiconductor channel and aresistor each formed from the same metal oxide. This enablesconsiderable cost and/or time savings during manufacture, as the numberof materials and methods used to form, pattern and define the circuitmay be minimised. The first quantity (100) of metal oxide, forming thefirst body (10), has been formed on a first region (51) of a substrate(5) which supports at least the transistor and resistor of the circuit.The first body (10) can thus be regarded as having been formed on orover a first region of a surface of the substrate (5). The secondquantity (200) of the metal oxide has been formed over a second region(52) of the substrate surface. The figure also illustrates a layer orbody of dielectric material (4) which has been formed over the first andsecond bodies (10, 20), the source and drain terminals and the resistorterminals, and which provides the gate dielectric of the transistor (1).The gate terminal (13) has then been formed over the layer of dielectricmaterial (4).

Although the embodiment of FIG. 1 shows the first and second bodies (10,20) each comprising the same metal oxide, the two quantities (100, 200)of metal oxide material have been deposited under different conditionssuch that the first body (10) exhibits substantially semi-conductivebehaviour, whereas the second body (20) exhibits substantially resistivebehaviour. It will be appreciated that this difference inelectrical/electronic properties can be achieved in a number of ways.For example, one of the quantities (100, 200) of metal oxide materialmay be deposited using a PVD technique in the presence of oxygen,whereas the other may be deposited by PVD not in an oxygen-containingenvironment. Alternatively, the different electrical/electronicproperties of the first and second bodies (10, 20) may be achieved byprocessing the first and second quantities (100, 200) differently, aftertheir initial formation/deposition stage, and such processing techniqueswill be described below. However, the embodiments of the invention arelinked by the novel concept of the transistor channel and resistor bodyboth comprising the same metal oxide material. In certain embodimentsthe transistor may be N-type (enhancement or depletion mode), whilst inothers it may be P-type (enhancement or depletion mode). In certainembodiments the transistor channel and resistor body both comprise, inplace of the metal oxide material, an organic material such as apolymer, a compound semiconductor, a 2D material such as graphene, or aperovskite.

In certain embodiments, the resistor (2) may be a load resistor,connected in series between one of the source and drain terminals and avoltage rail. FIG. 2 shows one such arrangement. Here the circuit module(10000) is a PMOS inverter (which may also be described as a NOT gate)with a resistive load. The resistor (2) is connected in series betweenthe transistor source (11) and a lower voltage rail (62), which isconnected to ground. The drain terminal of the transistor (12) isconnected to the high voltage rail (61) (Vdd).

FIG. 3 illustrates another circuit module embodying the invention, wherethe resistor (2) is connected on the high side of the transistor, inseries between voltage rail (61) and the drain terminal (12) of thetransistor (1). This circuit can be described as an NMOS invertercircuit or circuit module, or equivalently a NOT gate with resistiveload.

Referring now to FIG. 4, this illustrates a circuit module in accordancewith another embodiment, where the difference in electrical/electronicproperties of the first and second bodies (10, 20) has been achieved, atleast in part, by depositing the first quantity (100) of metal oxidematerial on a source of a first dopant (71) which has been formed on afirst region (51) of the substrate (5) the source of dopant (71) isarranged such that the first quantity (100) of metal oxide material maybe deposited as a resistive layer, with the pre-patterned dopantselectively causing the resistive layer deposited on top of it to becomesemi-conductive. The second quantity of metal oxide material (200) hasbeen deposited as a resistive layer on a second region (52) of thesubstrate (5) where no dopant source is present. Thus, this secondquantity (200) remains resistive, rather than being converted tosemi-conductive.

Referring now to FIG. 5, this shows an alternative embodiment in which asource of a second dopant (72) has been selectively provided over asecond region (52) of the substrate (5). The first and second quantities(100, 200) of metal oxide material have each been deposited initially assemi-conductive layers. However, the source of the second dopant (72)has been selected such that the dopant interacts with the secondquantity (200) to change its electrical properties from substantiallysemi-conductive to substantially resistive, and so results in the secondbody (20) being resistive, whereas the first body (10) remainssemi-conductive, and forms the channel of the transistor (1).

Although the examples discussed above in reference to FIGS. 4 and 5comprise a source of dopant (71, 52) beneath the semiconducting and/orresistive bodies (10, 20), a source of dopant may instead, oradditionally, be provided above or to the side of one or both of thosebodies. For example, a dielectric layer (4) may be a source of dopant,and/or the source and drain terminals (11, 12) and/or resistor terminals(21, 22) may be a source of dopant. The source of dopant may remain inthe final circuit structure or it may be removed during processing. Forexample a conductive layer used to form the source and drain terminals(11, 12) and/or resistor terminals (21, 22) may be a source of dopant,and doping of the semiconducting and/or resistive bodies (10, 20) may beachieved prior to partial removal of the conductive layer duringformation of the terminals, for example by patterning and etching.

It will be appreciated that whilst selective doping of the depositedquantities of metal oxide material may be used to achieve theirdifferent electrical properties, this technique may also be used inconjunction with depositing the first and second quantities (100, 200)under different conditions in certain embodiments. However, in otherembodiments, the first and second quantities (100, 200) may be depositedunder the same conditions, and their different electrical properties maybe achieved wholly by their different subsequent processing.

Referring now to FIG. 6, this illustrates a step in the manufacture ofanother electronic circuit module embodying the invention. Here, thestructures of the transistor (1) and resistor (2) have been formed,initially by depositing the first and second quantities (100, 200) ofmetal oxide material on respective portions of a surface of thesubstrate (5). These first and second quantities (100, 200) areinitially semi-conductive. They may, for example, be formed such thatthey are initially in a semiconductive “normally off” state (i.e. havinglow conductivity). However, the step illustrated in FIG. 6 is one inwhich the second quantity (200) of material is being selectively exposedto electro-magnetic radiation to change its conductivity. For example,the electro-magnetic radiation may be arranged so as to anneal at leasta portion of the second quantity of material and increase its electricalconductivity (e.g. relative to the low conductivity “off” state) suchthat it provides a resistive, rather than semi-conductive, path betweenits terminals. It will be appreciated that this selective exposure ofjust one of the bodies of metal oxide material (100, 200) may beachieved in a variety of ways. For example, radiation may be directed onto a wide portion of the circuit, with the gate terminal (13) acting asa mask to shield the first quantity of metal oxide material (100) (or atleast a substantial part of it) from the effects of the radiation.Alternatively, a separate mask may be used, and/or a source ofelectro-magnetic radiation may be used which is able to illuminate justa small part of the circuit (for example a laser beam may be used toperform the selective annealing/processing). Techniques suitable for usein certain embodiments, to increase the conductivity of one or more ofthe bodies, are described in U.S. Pat. No. 10,204,683B2.

Referring now to FIG. 7, this shows two steps in another methodembodying the invention. In this method, the first (100) and second(200) quantities of the metal oxide material have been deposited onseparate regions of the substrate (5), and initially both aresemi-conductive. For example, the first and second quantities may beformed so as to be semi-conductive, in a “normally off” condition (e.g.for IGZO devices that are n-type enhancement mode/positive thresholdvoltage). For such materials, since their conductivities are initiallyvery low (because they are in the “off” state), processing arranged toincrease their conductivities would be needed in order to change theirelectrical characteristics to resistive). The quantities of metal oxidematerial may, in certain embodiments, be formed as p-type “normally off”material, e.g. in SnO with a negative threshold voltage. NiO can also betuned from p-type to n-type with an increase in conductivity. Inalternative embodiments, the quantities of metal oxide material may beformed so as to be semi-conductive, in a “normally on” state (e.g. fordevices that are p-type with a positive threshold voltage). For suchmaterials, since their conductivities are initially relatively high(because they are in the “on” state), processing arranged to decreasetheir conductivities would be needed in order to change their electricalcharacteristics to resistive). Returning to the current embodiment, itwill be appreciated that the separate quantities (100, 200) shown inFIG. 7a may be produced by first depositing a uniform layer, sheet, orother structure of metal oxide material, and then patterning it by anysuitable means. Alternatively, the separate quantities (100, 200) may beselectively formed by any suitable technique on the substrates surface(for example by selective deposition, coating, printing, or otherwise).In the step illustrated in FIG. 7a , the second quantity (200) of metaloxide material is being selectively exposed to electro-magneticradiation so as to increase its conductivity, and change its electricalcharacteristics from being substantially semi-conductive (“normally off”semi-conductive material) to being resistive. After this exposure, whichcan generally be regarded as processing the second quantity (200) ofmetal oxide material differently from the first quantity (100), we havethe structure shown in FIG. 7b , where a semi-conductive body (10) ofthe metal oxide occupies one portion of the substrate surface, and thesecond body (20) of the substantially resistive metal oxide materialoccupies another portion. It will be appreciated that theterminal/contacts of the transistor and resistor may then be built up bysuitable processing techniques, and the gate dielectric and gateterminal can also be formed. Thus, the method illustrated in FIG. 7 isone in which the first and second quantities (100, 200) of metal oxidematerial are processed differently before the remainder of thetransistor and resistor are formed (in contrast to the methodillustrated in FIG. 6, where that different processing is performedafter the formation of the transistor and resistor structures).

Referring now to FIG. 8, this shows two steps in an alternative methodembodying the invention. Here, in FIG. 8a , an initially uniform layerof semi-conductive material (1200) has been formed to cover an opensurface of the substrate (5). Separate portions of that layer (1200)provide the first and second quantities (100, 200) of metal oxidematerial. FIG. 8a also illustrates that the second quantity (200) ofmetal oxide is being selectively exposed to electro-magnetic radiationto change its conductivity (for example to increase its conductivity,and hence decrease its resistivity, or decrease its conductivity andincrease its resistivity). It will be appreciated that this selectiveexposure may be performed by a variety of suitable techniques, as willbe apparent to the skilled person from their general knowledge in thisfield, as well as from the remainder of this specification. Thus, inthis example the selective processing of the second quantity (200) ofmetal oxide is performed before the layer (1200) is patterned. FIG. 8bshows the structure resulting from patterning the layer (1200), byselectively removing portions of it to expose underlying portions of thesubstrate (5) surface. In particular, metal oxide material has beenremoved to leave just the first and second bodies (10, 20). The firstbody (10) corresponds to the first quantity (100) of metal oxide, asdeposited as part of the initial layer (1200). The second body (20)comprises the second quantity (1200), which has also been exposed toelectro-magnetic radiation, and is now resistive rather thansemi-conductive. Again, after the two steps shown in FIG. 8, the furtherfeatures of the transistor and resistor will be built up by suitabletechniques.

Referring now to FIG. 9, this illustrates another circuit moduleembodying the invention. This circuit module comprises a transistor (1),a first resistor (2), and a second resistor (3). The transistor channelis provided by a first body of metal oxide material (10) formed on thefirst region (51) of the substrate (5). The first resistor (2) comprisesa resistive body (20), formed on a second region (52) of the substrate,and the second resistor (3) comprises a third body (30) of the samemetal oxide material as that forming the first and second bodies (10,20), this third body (30) being formed on a third portion of thesubstrate (53). The second resistor also includes resistor terminals (31and 32). In this embodiment, each of the first, second, and third bodies(10, 20, 30) is formed from the same metal oxide material. However, thefirst body (10) has been deposited under different conditions than thesecond body (20), so that the first body (10) is substantiallysemi-conductive, and the second body (20) is substantially resistive. Incertain embodiments, the third body (30) may have been deposited underthe same conditions as the second body (20), and may thus have the samesheet resistance. However, the geometries of the first and secondresistors (2, 3) may be different such that the first and secondresistors exhibit different resistances from each other. In alternativeembodiments, however, the second and third bodies (20, 30) may bedeposited under different conditions such that the sheet resistances oftheir resistive bodies (20, 30) may be different. Thus, differentresistances may be achieved even though the geometries of the first andsecond resistors are not necessarily different from each other. Clearly,in yet further embodiments, a combination of different resistorgeometries (e.g. different resistive path lengths and widths) may beemployed in addition to different deposition techniques to yieldresistors having different values in the electronic circuit.

Referring now to FIG. 10, this illustrates the step in the formation ofanother circuit module embodying the invention. In this embodiment, thecircuit module again comprises a transistor (1) and first and secondresistors (2, 3) formed on a common substrate (5). The transistor (1)comprises a semi-conductive channel provided by a first quantity (100)of metal oxide material. This first quantity (100) has been deposited atthe same time as depositing second and third quantities (200, 300) ofthe metal oxide material under the same conditions. The conditions havebeen selected such that these first, second, and third quantities (100,200, 300) are each initially semi-conductive. FIG. 10 illustrates a stepin which conductivities of the second and third quantities (200, 300)are changed, whereas the conductivity of the first quantity (100)remains as initially deposited. In particular, electro-magneticradiation (labelled R) is being directed at the illustrated structure,and the gate terminal (13) acts as a mask to shield the first quantity(100) of metal oxide material from that radiation and its effects. Incontrast, the third quantity (300) is fully exposed to the radiation R,is annealed (or otherwise affected) by exposure to that radiation, andhence the initially semi-conductive (e.g. normally off) material of thatthird quantity (300) is converted to resistive material (by having itsconductivity increased). The figure also shows a partial mask being usedto absorb just a portion of the radiation directed towards the secondquantity (200) of metal oxide material. In other words, the partial maskpartially shields the second quantity of material (200) from theradiation R. Thus, the second quantity (200) of metal oxide is annealed(or otherwise affected) to a lesser extent than the third quantity(300), and hence sees a correspondingly smaller, but still significant,increase in its conductivity. Thus, the techniques illustrated in FIG.10 are able to yield a circuit module with a semi-conductive transistorchannel, and first and second resistors having different resistances,all being formed from the same metal oxide material, but processeddifferently to yield different electrical properties.

Referring now to FIG. 11, this shows another embodiment incorporating atransistor (1) and first and second resistors (2, 3). In this example,the semi-conductor channel (10) and the second and third resistor bodies(20, 30) have all been deposited at the same time from the same metaloxide material under the same deposition conditions, such that thefirst, second, and third quantities (100, 200, 300) of metal oxidematerial are each initially semi-conductive. However, the secondquantity (200) has been formed on a second dopant source (72), and thethird quantity (300) has been formed on a third dopant source (73). Thedopant materials and/or their concentrations have been selected suchthat they result in the second and third bodies (20, 30) beingdifferently doped, and hence exhibiting different resistances. No dopantis provided to the first quantity of metal oxide material, whichaccordingly simply provides the first body (10) of the transistor (1).

Referring now to FIG. 12, this shows steps in another method embodyingthe invention in which the first and second quantities (100) of metaloxide material are deposited at different stages in the manufacturingmethod, and under different conditions to achieve differentconductivities of the bodies (10, 20) formed from the same metal oxidematerial. FIG. 12a shows how an initial layer (1001) of metal oxidematerial has been formed over a substrate (5), which in certainembodiments is flexible, and in alternative embodiments is rigid. Thesubstantially uniform layer (1001) comprises the first quantity (100) ofmetal oxide material that will form the basis of the channel of thetransistor. The structure shown in FIG. 12a is then patterned bysuitable means to yield the structure shown in FIG. 12b . Thus, portionsof the layer (1001) have been selectively removed to leave just thefirst quantity (100) of metal oxide material that will form the firstbody (10). It will be appreciated that a wide variety of techniques maybe used to perform this patterning, for example techniques involving oneor more of the following: lithography, photolithography, imprinting,nano-imprinting. In the illustrated method, a layer of conductivematerial (81) is then formed over the first body (10) and substrate (5).Using suitable techniques, that conductive layer (81) is patterned toform the source and drain terminals (11 and 12) and first and secondterminals (21, 22) of the resistor. A layer of resist material (9) isthen formed over the terminals/contacts and semi-conductive channel, toyield the structure shown in FIG. 12d . Again, by using suitabletechniques, a window (90) is formed in the resist layer (9), exposing atleast part of the resistor terminals (21, 22) and a portion of thesubstrate surface extending between them. Then, FIG. 12f illustrates theformation (by deposition or otherwise) of a second layer (2001) of thesame metal oxide material as the first layer (1001), but under differentconditions such that the second layer (2001) exhibits resistivebehaviour rather than semi-conductive behaviour. This second layer(2001) includes the second quantity (200) of metal oxide material, whichforms the second body (20) of the resistor, providing a resistive pathbetween the resistor terminals (21, 22). Thus, in this example theresistor has bottom contacts i.e. its terminals are formed directly onthe substrate surface and the resistive body (20) is formed so as tooverlap those resistor terminals on top. FIG. 12g illustrates a furtherstep, where the remaining resist material of the layer (9) has beenremoved and FIG. 12h illustrates the final structure resulting fromformation of the dielectric layer (4) over the structure shown in FIG.12g , and then formation of a gate electrode (13) over the transistorchannel body (10). Thus, in the embodiment illustrated in FIG. 12, thechannel body (10) and resistor body (20) have been formed from differentlayers of metal oxide material, those different layers having beenformed under different conditions such that the channel (10) exhibitssemi-conductive behaviour and the resistor body (20) exhibits resistivebehaviour.

Also, in the embodiment shown in FIG. 12, the resistor body (20) hasbeen formed after formation of the conductive contacts of both thetransistor and resistor.

Referring to FIG. 13, this shows an alternative technique where thefirst and second bodies are formed at different times, but beforeformation of the conductive contacts. FIG. 13a shows the initialformation of a first layer (1001) of metal oxide material including thefirst quantity (100), on top of the substrate (5). By suitabletechniques this layer (1001) is patterned to yield the structure shownin FIG. 13b , comprising the first quantity (100) of metal oxidematerial on the substrate. Then, in FIG. 13c , the second quantity ofmetal oxide material (200) has been formed on a different region of thesubstrate, after formation of the first quantity (100).

Referring now to FIG. 14, this shows an alternative method in which thesecond quantity of metal oxide material (200) is formed initially on thesubstrate surface. Then, as illustrated in FIG. 14b , the first quantity(100) is formed on a different portion of the substrate, after formingthe second quantity (200).

Referring now to FIG. 15, this illustrates yet another method of formingan electronic circuit module embodying the invention. As shown in FIG.15a , a layer (2001) of metal oxide material is first formed on thesubstrate (5), that layer (2001) comprising the second quantity of metaloxide material (200) which will form the body of the resistor. Usingsuitable techniques, that layer (2001) is patterned, to yield thestructure shown in FIG. 15b . This second quantity (200) has been formedunder conditions such that the metal oxide material exhibits resistivebehaviour. Then, as shown in FIG. 15c , a layer of resist material (9)has been formed. Then, as shown in FIG. 15d , a window (90) has beenformed in the resist layer (9), and a layer (1001) of metal oxidematerial has been deposited, so as to cover the portion of substrateexposed by the window (90) with a first quantity of metal oxide material(100). The formation conditions of the layer (1001) are such that thisfirst quantity (100) is substantially semi-conductive, in contrast tothe resistive second quantity (200), even without any subsequentprocessing. The remaining resist material is then removed by suitabletechniques, and a layer of conductive material (81) is formed on top ofthe underlaying structure, to yield that illustrated in FIG. 15e . Thatconductive layer (81) is then patterned to yield the structure shown inFIG. 15f , comprising the transistor source and train terminals and thefirst and second resistor terminals (21, 22). It will be appreciatedthat the other components of the circuit module may then be built up ontop of this structure, using appropriate techniques.

Referring now to FIG. 16, this illustrates part of another circuitmodule embodying the invention. In this example, each of the first andsecond bodies (10, 20) is being formed from a layer, sheet, or film ofmetal oxide material. In this example, the thickness of that layer, filmor sheet is T. Thus, the first and second bodies (10, 20) each have thesame thickness. However, the semi-conductive channel provided by thefirst body (10) has length L1, and the resistive path provided by thesecond body (20) has length L2, where L1 is different from L2. Incertain alternative embodiments, however, it will be appreciated thatthe channel and resistive path may have the same length as each other.

Referring now to FIG. 17, this illustrates yet another embodiment, wherethe first body (10) has thickness T1, and the second body (20) has adifferent thickness T2. Again, the length L1 of the channel and thelength L2 of the resistive path are different.

It will be appreciated from FIGS. 16 and 17 that, in certainembodiments, the first and second bodies (10, 20) are formed ondifferent respective areas of a surface of the substrate (5), and thenthe contacts or terminals (11, 12, 21, 22) are formed subsequently, soas to overlap upper surfaces of the first and second bodies (10, 20).FIG. 18 illustrates an alternative embodiment, in which the source anddrain terminals (11, 12) and first and second resistor terminals (21,22) have been formed on the substrate (5) before formation of the firstand second bodies (10, 20). Thus, the first body (10) partially overlapsthe source and drain terminals (11, 12) in this example, and the secondbody (20) also partially overlaps upper surfaces of the resistorterminals (21 and 22). A gate dielectric (4) has been formed over thefirst body (10) and terminals (11, 12), and a gate terminal (13) hasbeen formed on top of the gate dielectric. Thus, it will be appreciatedfrom FIG. 18 that the first body (10) and/or second body (20) are notnecessarily planar in all embodiments of the invention. This is furtherillustrated by FIG. 19, which shows a circuit module embodying theinvention where the first body (10) has been formed initially on asurface of the substrate (5), under conditions such that its behaviouris semi-conductive. The source and drain terminals (11, 12) and firstresistor terminal (21) have then been formed at the same time, with thesource and drain terminals (11, 12) partially overlapping upper surfacesof the first body (10). The first resistor terminal (21) is formeddirectly on a portion of the surface of the substrate (5). The secondbody (20) has been formed in a subsequent step (i.e. after formation ofthe first body (10)), under conditions such that it exhibits resistivebehaviour, and that second body (20) covers at least part of the uppersurface of the first resistor terminal (21) and a portion of thesubstrate surface (5) adjacent that first terminal (21). The secondresistor terminal (22) has been formed later, and sits on top of thesecond body (20). Thus, the resistor body (20) is again not simplyplanar. In this example, it is stepped, and the first and secondresistor terminals (21, 22) have been formed in different steps (ordifferent sequences of steps) i.e. from different conductive layers.Thus, the resistor terminals, in this example, are not formed at thesame time (or in the same processing step or sequence of steps) as eachother.

Referring now to FIG. 20, this shows an alternative circuit embodyingthe invention where the transistor (1) has a bottom gate structure, andthe resistor has bottom contacts. It will be appreciated that thestructure shown in FIG. 20 may be formed by a method in which the gateand resistor contacts (21 and 22) may be formed at the same time, forexample by the patterning of an initially continuous layer of conductivematerial formed on a surface of the substrate (5), the resistive body(20) may then be formed form metal oxide material under conditions suchthat it exhibits resistive behaviour. Then, the gate dielectric may beformed before forming the channel body (10) above the gate, this timeunder conditions such that the channel body (10) is semi-conductiverather than resistive. The source and drain contacts (11, 12) may thenbe formed, by suitable techniques. In this example the first body (10)and second body (20) are not coplanar, however their respective planesof orientation are parallel to each other.

Referring now to FIG. 21, this illustrates an alternative circuit moduleembodying the invention, where the transistor (1) has a bottom gatestructure, and the resistor has overlapping top contacts (21, 22). Toform the structure of FIG. 21, the gate terminal may first be formed.Then the resistor body (20) may be formed, before or after formation ofthe gate dielectric. The transistor body (10) is then formed after theresistor body (20), and the source and drain terminals (11, 12) andresistor terminals (21, 22) may be formed in different steps or at thesame time as one another, for example by patterning a layer ofconductive material.

Referring now to FIG. 22, this shows an alternative embodiment in whichthe first and second quantities (100, 200) of metal oxide material havebeen formed at the same or different times, under the same or differentprocessing conditions. However, the first quantity (100) has been formedover a first dopant source (71) and the second quantity (200) has beenformed over a second dopant source (72). The dopant materials and/ortheir concentrations have been selected such that the interaction of thefirst quantity of metal oxide material (100) with the first dopantsource (71) results in the first body (10) being semi-conductive, andthe interaction of the second quantity of metal oxide material (200)interacts with the second dopant source (72) such that the second body(20) provides a resistive current path between the terminals (21, 22).

FIG. 23 illustrates a similar embodiment in which the substrate (5)itself has been doped selectively in different regions to provide thedifferent dopant sources (71 and 72) which interact with the first andsecond quantities (100, 200) to yield a semi-conductive channel andresistive body respectively.

Referring now to FIG. 24, the is illustrates steps in a further methodembodying the invention. In step 24 a, a layer of metal oxide material(1200) has been formed on a surface of the substrate (5), that layer(1200) comprising first and second quantities (100, 200) of metal oxidematerial. That structure is then patterned by suitable technique toyield the structure shown in FIG. 24b , a layer of conductive material(81) is then deposited over that structure to yield the structure shownin FIG. 24c , and that layer (81) is then patterned by suitabletechniques to yield the structure shown in FIG. 24d , with portions ofthe previous conductive layer (81) forming the resistor terminals (21,22) and source and drain terminals (11 and 12), each of those terminalspartly overlapping an upper surface of the respective quantity (100,200) of metal oxide material. A layer of dielectric material (4) is thenformed to yield the structure shown in FIG. 24e , and a second layer ofconductive material (82) is formed on top, that layer (82) comprisingthe material which will form the gate terminal (13). That second layeris then patterned by suitable techniques to yield the structure shown inFIG. 24g , with the gate terminal (13) above the semi-conductive channelbody (10). At the stage illustrated in FIG. 24g , each of the quantities(100, 200) may be substantially semi-conductive (e.g. “normally off”semiconductor material), FIG. 24h shows a subsequent step in which thestructure of FIG. 24g is exposed to electro-magnetic radiation R tothermally anneal (or otherwise affect) just the second quantity (200) ofmetal oxide material, increasing its conductivity and changing itsproperties from semi-conductive (normally off) to resistive. The gate(13) acts as a mask or shield, and shields the first quantity (100) fromthe radiation R such that it is substantially unaffected by theradiation and hence the transistor body (10) exhibits semi-conductivebehaviour rather than resistive. Advantageously, this embodiment is onein which the metal oxide material for the transistor channel andresistor body may be deposited at the same time. The difference ineventual electrical properties of the channel and resistor body areachieved by the different subsequent processing.

It will be appreciated that although certain embodiments provideflexible electronic circuits, such as flexible ICs, and/or low costcircuits, other embodiments may provide circuits, such as ICs, that arenot flexible, nor necessarily low cost, for example those manufacturedon rigid substrates or part-complete systems.

Any suitable material(s) may be used as a substrate (5), which may becomposed from one or more layers of such materials. The substrate (5)may be flexible, comprising any one or more materials from the followinglist: Glass (rigid or flexible); polymer (e.g. polyethylene naphthalate,polyethylene terephthalate; polymethyl methacrylate; polycarbonate,polyvinylalcohol; polyvinyl acetate; polyvinyl pyrrolidone;polyvinylphenol; polyvinyl chloride; polystyrene; polyethylenenaphthalate; polyethylene terephthalate; polyimide, polyamide (e.g.Nylon); poly(hydroxyether); polyurethane; polycarbonate; polysulfone;parylene; polyarylate; polyether ether ketone (PEEK); acrylonitrilebutadiene styrene; 1-Methoxy-2-propyl acetate (SU-8); polyhydroxybenzylsilsesquioxane (HSQ); Benzocyclobutene (BCB)); Al2O3, SiOxNy; SiO2;Si3N4; UV-curable resin; Nanoimprint resist; photoresist; polymericfoil; paper; insulator-coated metal (e.g. coated stainless-steel);cellulose.

Any suitable material(s) may be used as a layer of dielectric material(4), which may be composed from one or more layers of such materials.Examples of suitable materials include: Metal oxides such as Al2O3,ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5; metal phosphates such as Al2POx;metal sulphates/sulphites such as HfSOx; metal nitrides such as AlN;metal oxynitride such as AlOxNy; inorganic insulators such as SiO2,Si3N4, SiNx; spin on glass (such as polyhydroxybenzyl silsesquioxane,HSQ), polymeric dielectric materials (such as Cytop, a commerciallyavailable amorphous fluoropolymer), 1-Methoxy-2-propyl acetate (SU-8),benzocyclobutene (BCB), polyimide, polymethyl methacrylate, polybutylmethacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinylpyrrolidone, polyvinylphenol, polyvinylchloride, polystyrene,polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicone; UVcurable resins; Nanoimprint resists; or photoresists. The dielectricmaterial may have a relatively low dielectric constant (low-K, e.g.Cytop, HSQ, parylene) or a relatively high dielectric constant (high-κ,e.g. Ta2O5, HfO2).

Any suitable material(s) may be used to form the transistor source,drain and gate terminals (11, 12, 13) and the resistor terminals (21,22), any of which may be composed from one or more layers of suchmaterials. Examples of suitable materials include: Metals, such as Au,Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys, such as MoNi,MoCr, AlSi; transparent conductive oxides, such as ITO, IZO, AZO; metalnitrides, such as TiN; carbon materials, such as carbon black, carbonnanotubes, graphene; conducting polymers, such as polyaniline,PEDOT:PSS; or semiconductor material.

Any suitable material may be used to form the first body (10) ofmaterial providing a controllable semi-conductive channel and the secondbody (20) of material providing a resistive current path, and any otherfurther semi-conductive and resistive bodies in the circuit. The firstbody (10) or the second body (20) or both bodies may be composed fromone or more layers of such materials. Examples of suitable materialsinclude metal oxides, such as ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO,ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO), AlZnO(AZO). Other suitable materials may include organic materials such aspolymers, compound semiconductors, 2D materials such as graphene, andperovskites. A suitable material is one that may be used to form aresistive body or a semi-conductive body depending on its stoichiometry,deposition, processing and/or doping. The first body (10) and secondbody (20) may both consist of the same material. In other embodimentseither the first body (10) or the second body (20) or both bodies (10,20) may each comprise an additional material that may be taken from theabove list or may be a different type of material such as a conductor,an insulator or a different type of semiconductor. Thus, another aspectof the invention provides an electronic circuit (or circuit module)comprising a transistor and a resistor, the transistor comprising asource terminal, a drain terminal, a gate terminal, and a first bodyproviding a controllable semiconductive channel between the source anddrain terminals, the resistor comprising a first resistor terminal, asecond resistor terminal, and a second body providing a resistivecurrent path between the first resistor terminal and the second resistorterminal, wherein said first body comprises a first quantity of amaterial and said second body comprises a second quantity of saidmaterial. Another aspect provides a method of manufacturing such acircuit, comprising forming said first body and forming said secondbody.

It will also be appreciated from the above-description that certainembodiments of the invention provide improvements to unipolar (i.e.based on either p-type or n-type semiconductors) circuits (e.g. FlexICs)to extend their capabilities for low cost processing, sensing,communication and other applications. The approach is based on theintegration of resistors into the circuits (e.g. FlexICs) along with theunipolar transistors. These resistors, in certain embodiments, have someor all of the following properties:

1. Used as a transistor load they enable FlexICs to incorporate logiccircuits of greater complexity and efficiency

2. Used in analogue circuits they enable timers and other essentialfunctions in, for example, RF circuits

3. They exhibit sheet resistance values of between approximately 50 kΩ/□and 10 MΩ/□

4. They may be fabricated using established thin-film depositiontechniques, e.g. PVD, CVD, etc.

5. They do not require post-deposition processing of either longduration or high energy consumption

6. They have a high optical transmittance, and may be substantiallytransparent

7. They are formed from a material composed of the same elements asthose in the semiconductor channel of the transistors (e.g. FlexIC'stransistors)

8. They are formed from a metal oxide (e.g. NiO, SnO, IGZO)

9. They are formed from Indium Gallium Zinc Oxide (IGZO)

10. They are located in one or more layers of the FlexIC

11. They are located in either the same or different layer(s) as thesemiconductor channel of the FlexIC's transistors

The present inventors are aware that electronic properties of metaloxides have been investigated with some intensity relatively recently.Much of this work has been in the context of (i) very low resistivity,for application as transparent conducting oxides such as indium tinoxide, or (ii) very high resistivity, for semiconductor applications.The present inventors appreciate that electromagnetic irradiation, suchas from a UV laser or lamp, may reduce the resistivity of a metal oxidesemiconductor material from the order of 10⁹ Ω/□ to around 10 ⁵ Ω/□.Accordingly, certain embodiments of the present invention useelectromagnetic irradiation to modify resistance for the purposes ofsetting the resistance of one or more resistors in a circuit (e.g. anIC).

Resistors in embodiments of the present invention are formed from metaloxides. Their resistivities may be determined primarily by thestoichiometry of the metal oxides, by the techniques and conditions usedto deposit and process them, and by the incorporation of elements fromneighbouring materials in the IC structure. For example, a pre-patterneddopant or one present in a layer above or beside the resistor mayselectively cause the metal oxide semiconductor film to become resistiveafter deposition and processing:

By depositing a quantity of initially semiconductive material on top ofa dopant (or source of said dopant), the dopant may then change thesemiconductive film to a resistive film. This technique is used incertain embodiments.

The dopant may donate atoms, e.g. O, H, F, N, Y, to the initiallysemiconductive layer, or alternatively the dopant may accept such atomsfrom the initially semiconductive layer to leave vacancies in thematerial (and so increase its conductivity/reduce its resistivity).Alternatively a metal oxide film may be deposited as a resistive layerwith a pre-patterned dopant selectively causing the resistive layer tobecome semiconductive.

In another example a semiconducting film may be formed from a materialhaving one stoichiometry (molar proportion of elements) whilst aresistive film may be formed from the same material having a differentstoichiometry.

Thus, to achieve a semiconductive channel and a resistive body, eachcomprising the same metal oxide, the respective quantities of metaloxide material may exhibit different stoichiometries and/or may beformed/deposited under different conditions and/or may be processeddifferently after being formed. Deposition/processing examples of how todifferentiate the resistive bodies from semiconductor channelscomprising the same metal oxide material can include the following,either individually or in combinations, and for a body comprising morethan one layer of material the deposition/processing may be differentfor each layer:

Deposition (e.g. of IGZO) by PVD or by ALD (atomic layer deposition) inthe presence, absence or different concentrations of O2, N2, F, H2

Deposition by PVD vs ALD

By thermal annealing, e.g. by annealing only resistive bodies orsemiconductor channels, or annealing both resistive bodies andsemiconductor channels in different conditions of temperature and/orpresence of air, O2, N2, Ar, H2, forming gas, etc.

By plasma treatment, e.g. CF4, Ar, O2, N2, NF3, H2, during or afterdeposition

By UV laser or excimer lamp (as noted above)

By controlling the thicknesses of the semiconductive channel and theresistive body.

It will be appreciated that although the above-mentioned techniques,materials, and configurations have been described in connection with themanufacture of circuit modules incorporating at least one transistor andat least one resistor, they may also be applied, mutatis mutandis, inthe manufacture of alternative circuit modules incorporating at leastone resistor and at least one Schottky diode, at least one transistorand at least one Schottky diode, or at least one each of a resistor,transistor, and Schottky diode.

Referring now to FIG. 25, this shows another circuit module embodying anaspect of the invention and incorporating a transistor 1 and resistor 2.The transistor in this example is a top-gate transistor, and theresistor is top-contact, i.e. with upper surfaces of its terminals 21,22 exposed for further connections. The structure is generally the sameas the embodiment shown in FIG. 1. The substrate 5 is here referred toas an underlayer and it will be appreciated that this may comprise oneor more layers, or may indeed comprise a complex structure(incorporating further electronic components and/or circuits forexample) upon which the resistor 2 and transistor 1 have been formed.The gate 13 in this example is stepped, partially filling a recess inthe dielectric layer 4 above the body 10 forming the semi-conductivechannel (which in this example is an n-type semiconductor).

FIG. 26 illustrates steps in a method of producing a circuit module suchas that shown in FIG. 25. FIG. 26A illustrates a first step in which aquantity of metal oxide material 200 is formed on the underlayer 5 underconditions such that it is generally resistive in its electricalbehavior. This quantity 200 thus forms the resistor body 20. Next, asshown in FIG. 26B, a further quantity 100 of metal oxide material isdeposited on the upper surface of the underlayer, this time underconditions such that the metal oxide material is semi-conductive, andforms the body 10 of the transistor. Next, as shown in FIG. 26C, a layerof conductive material 81 is formed over the first and second bodies 10,20 and the upper surface of the substrate 5, and then that conductivelayer 81 is patterned using a suitable technique to yield the structureshown in FIG. 26D which includes the transistor and resistor terminals11, 12, 21, 22. Next a layer of dielectric material 4 is formed over theunderlying structure, as shown in FIG. 26E and then the gate terminal 13is formed over the semi-conductive channel 10, as shown in FIG. 26F.Also, the dielectric layer 4 has been processed so as to exposure uppersurfaces of the resistor terminals 21, 22.

Whilst this top-contact, top-gate structure is appropriate for use incertain embodiments, there can be issues with the patterning of multiplemetal oxide (e. g. IGZO) layers, and there may be the need to separateproduction of the semi-conductive body 10 and resistor body 20. Also, incertain examples the semi-conductive material 10 may interact with theunderlayer and this can be undesirable. Furthermore, it is desirable forcertain applications to integrate Schottky devices in circuit modulesincorporating a resistor and/or a transistor, and this may require theprovision of a bottom-electrode. The integration of Schottky devices incircuit modules embodying certain aspects of the invention is desirablein order to produce lower footprint near field communication (NFC)circuits, to produce lower power circuits, to produce higher speedcircuits (e. g. circuits able to operate at UHF frequencies), and alsoto take into account ESD protection factors.

With these considerations in mind, FIG. 27 illustrates another circuitmodule embodying an aspect of the invention. This can be regarded as atop-contact, bottom-gate module. Here, the transistor gate 13 has beenformed on an upper surface of the substrate 5, as has the resistor body20. The resistor body can be formed before or after the bottom gate 13,and this may enable the processing on the resistor body to be minimized.A first layer of dielectric material 41 has been formed over the gate13, this layer 41 also covering the upper surface of the resistor body20. The semi-conductive body 10 of the transistor 1 has been formed onthis first dielectric 41, and then the transistor source and drainterminals 11, 12 have been formed so as to partially overlap the uppersurface of the semi-conductive body 10. A further layer of dielectricmaterial 42 has been formed, but leaves upper surfaces of the transistorand resistor terminals 11, 12, 21, 22 exposed for further connections.

Although the n-type semi-conductive channel 10 in this figure isillustrated as a single body, it will be appreciated that in certainembodiments this semi-conductive body 10 can be engineered, for example,to include a graded channel or a plurality of different layers (forexample, high-low resistance layers etc.). In other words, thesemi-conductive body 10 in this embodiment, and indeed in otherembodiments, may consist of two or more layers of semi-conductor, eachhaving tailored conductivity, mobility, carrier concentration etc.

The transistor source and drain terminals 11, 12 may be produced byvarious suitable techniques, for example, including masking and etching,or patterning a resist layer, forming windows, depositing conductivematerial inside the windows, and then lifting off remaining resistmaterial. The second dielectric material may be patterned using varioussuitable techniques. Furthermore, although a simple lateral resistor 2is shown in the figure, other forms of resistor may be incorporated inalternative circuit modules embody the invention, (for example, verticalresistors, resistors with terminals offset both horizontally andvertically, etc.).

FIG. 28 illustrates some of the steps in the formation of a circuitmodule such as that shown in FIG. 27. FIG. 28A illustrates the provision(by deposition or otherwise) of a quantity 200 of metal oxide materialon a nominal upper surface of the substrate 5. This quantity 200 may beprovided in an initial state in which it exhibits generallysemi-conductive behavior. FIG. 28A illustrates, with the large arrow, anexposure of that body 200 of initially semi-conductive material toelectromagnetic radiation of suitable frequency to change the electricalproperties of the body from semi-conductive to resistive, as describedabove in relation to other embodiments. Then, FIG. 28B illustrates afurther stage in the method in which resistor terminals 21, 22 have beenformed at the same time as forming the bottom gate electrode 13. Thus,in this example the resistor terminals 21, 22 and gate terminal 13 areformed from the same conductive material (e. g. a metal).

FIG. 28C illustrates a later stage in the method, in which the firstdielectric layer 41 has been formed over the resistor and gateelectrode, the semi-conductive body 10 has been formed on the firstdielectric 41, the transistor source and drain electrodes 11, 12 havethen been formed, and then a second dielectric layer 42 has been formedover the underlying structure. In certain examples the upper dielectriclayer 42 may be left in this form or, alternatively, it may be patternedto exposure surfaces of one or more of the previously underlyingterminals.

As described above, for certain applications is it desirable tointegrate a Schottky diode in an integrated circuit comprising at leaston transistor and/or at least one resistor as described above. It willbe appreciated that the above teachings regarding the production ofelectronic circuit modules comprising at least one resistor may beapplied to the production of circuit module embodying other aspects ofthe invention and incorporating a Schottky diode and at least onetransistor and/or at least one resistor, making the appropriate changes.

FIG. 29 illustrates one such circuit module embodying the invention.This circuit module is similar to that illustrated in FIG. 27 (i. e. atop-contact, bottom-gate module) but, additionally, incorporates aSchottky diode 3000. This Schottky diode comprises a first electrode3001, which in this example is formed of an upper surface of thesubstrate 5, like the bottom-gate 13 of the transistor 1. The diodeincludes a body of semi-conductive material 2010 connected between thefirst electrode 3001 to second electrode 3002. The interface or junctionbetween the first electrode 3001 and the diode body 3010 is arranged toprovide a Schottky (rectifying) contact, and the interface or junctionbetween the diode body 3010 and the upper electrode 3002 is arranged tobe ohmic. However, it would be appreciated that the alternativeembodiments the upper contact may be a rectifying contact, and the lowercontact may be ohmic, to suit requirements. Again, the circuit modulecomprises a first dielectric layer 41, and a second dielectric 42 whichis arranged so that no upper surface of either of the transistor body 10or diode body 3010 is exposed.

Referring now to FIG. 30, this illustrates steps in the manufacture of acircuit such as that shown in FIG. 29. In FIG. 30A the resistor body 20has been formed on an upper surface of the substrate 5, and a conductivelayer 81 has been formed over the top. That conductive layer has thenbeen patterned to yield the resistor terminals 21, 22, the gate terminal13 and the diode lower electrode 3001. Then, in FIG. 30C, a firstdielectric layer has been formed over the underlying structure andpatterned to form a window exposing part of an upper surface of thediode lower electrode 3001. In this example the conductive layer 81consists of titanium (Ti). In the step illustrated in FIG. 30C theexposed upper surface of the Ti electrode 3001 is oxidized by baking inair at 200° c. to create TiOx. That TiOx layer is illustrated as 3011 inthe figure. FIG. 30D illustrates a further stage in the manufacturingprocess, in which the diode body 3010 has been formed by depositing afurther quantity 3100 of metal oxide material so as to fill the windowin the dielectric layer 41 and extend along an upper surface of thatlayer 41. The interface between the metal oxide material of the diodebody 3010 and the oxidized surface of the lower electrode 3001 providesthe rectifying Schottky contact. A further layer of conductive material810 has been formed over the structure and that layer is then patternedto yield the structure illustrated in FIG. 30E, with remaining portionsof that further conductive layer 810 providing the transistor terminals11, 12 and upper terminal 3002 of the Schottky diode. Thus, in thisembodiment, the diode body 3010 has been formed at a different time tothe formation of the resistor body 20 (in this case after). The diodebody 3010 may be formed at the same time as forming the transistor body10 (e.g. under the same process conditions), or may be formed at adifferent time to the transistor body (e.g. under different processconditions, if the diode and transistor bodies are required to havedifferent electrical properties, or if separate formation isadvantageous/desirable for other reasons).

It will be appreciated from FIGS. 29 and 30 that certain embodiments ofthe invention comprise a Schottky diode incorporating both a verticaland horizonal offset between its terminals, but it will also beappreciated that certain alternative embodiments may incorporateSchottky diodes having purely vertical or purely horizontal structuresas is known in the art. In certain embodiments it is possible to repairresistive TIOX on an electrode surface, for example, using CF₄/O₂ or aCl etch.

Referring now to FIG. 31, this shows another circuit module embodyingthe invention, this time comprising a top-contact, dual-gate transistor1, a Schottky diode 3000 and a resistor 2. It is similar to theembodiment shown in FIG. 29, but the transistor 1 comprises anadditional top-gate 132 (the previous gate now being labelled as thelower gate 131). Thus, the conductive properties of the semi-conductivebody 10 can be controlled by application of suitable voltages to boththe lower gate 131 and the upper gate 132. Such embodiments findparticular application in analogue circuits, and provide additionalcontrol of transistor threshold-voltage, by provision of the extra gate.The circuit may be arranged, in use, such that the same voltage isapplied to both the lower and upper gates 131 and 132, or separatevoltages may be applied to the top gate and the bottom gate. Theprovision of the dual-gate transistor can enable the higher mobility tobe achieved, and enable the transistor to conduct larger currents.

Referring now to FIG. 32, this illustrates yet another circuit moduleembodying the invention, comprising a Schottky diode 3000, a firsttransistor 1A having an n-type semi-conductive body/channel 10A, and asecond transistor 1B having a p-type semi-conductive body/channel 10B.Although the illustrated module incorporates transistors having just asingle gate each, it will be appreciated that additional gates may beemployed in one or both of the transistors 1A, 1B, making them dual-gatetransistors. In this example, the p-type semi-conductive layer 10B hasbeen formed partly in contact with an upper surface of the substrate 5,partially overlapping terminals 11B and 12B of the second transistor 1B.The gate 13A of the first transistor 1A is also formed on that uppersurface of the substrate 5, as is the first electrode 3001 of the diode3000. These various electrodes may all be formed at the same time, forexample, from a common sheet of conductive material, or may be formed indifferent steps, for example, if the conductive material required forthe diode first electrode 3001 is different from the material requiredfor the transistor electrode. It will be appreciated that the circuitmodule illustrated in FIG. 32 represents the provision of CMOStechnology together with a Schottky diode in an integrated circuit.

FIGS. 33-35 illustrate various electronic circuits or circuit modulesembodying the invention and incorporating different combinations ofSchottky diodes and/or resistors and/or transistors.

Referring now to FIGS. 33 to 35, it will be appreciated that variouscircuits and circuit modules embodying the present invention maycomprise combinations of at least one transistor and/or at least oneresistor and/or at least one Schottky diode, for example in the form offlexible integrated circuits/modules. Such circuits/modules includelogic gates. Such logic gates may comprise one or more diodes, either asthe sole active elements (e.g. in “diode logic”) or in combination withtransistors (“diode-transistor logic”). Two diode logic examplesembodying the invention and incorporating Schottky diodes are shown inFIGS. 33 and 34. FIG. 33 illustrates a diode OR gate embodying an aspectof the invention, and comprising two diodes, each having a respectiveanode connected to a respective input terminal, and a respective cathodeconnected to an output terminal. The output terminal is connected toground via a resistor. FIG. 34 illustrates a diode AND gate embodying anaspect of the invention, and comprising two diodes, each having arespective cathode connected to a respective input terminal, and arespective anode connected to an output terminal. The output terminal isconnected to a positive supply rail 1000 via a resistor. The use ofSchottky diodes in logic gates (as in these embodiments, for example)may provide advantages of fast response and small voltage drop, as wellas other benefits.

Another circuit module embodying the invention is a diode load inverter,as illustrated in FIG. 35. A conventional unipolar inverter typicallyplaces a transistor switch and resistor load between high and lowvoltage references. The inverter input is connected to the transistorgate terminal, and the inverter output is connected to the junction ofthe transistor and the resistor. In a diode load inverter, the resistorload is replaced by a diode, for example as shown in FIG. 35. The use ofa Schottky diode as a load in a diode load inverter, such as shown inFIG. 35, may provide benefits of fast switching, low voltage drop andlow power consumption, among others.

Referring now to FIG. 36, this illustrates a basic CMOS invertor whichmay be implemented in an integrated circuit having the structure of thefirst and second transistors 1A, 1B as illustrated in FIG. 32.

As will be appreciated from the above, certain circuit modules embodiedin the invention incorporate dual-gate transistors, having top andbottom gates on either side of a semi-conductive channel or body 10.Indeed, a further aspect of the present invention provides a dual-gatetransistor and an embodiment of this aspect is illustrated in FIG. 37.Here, the transistor 1 comprises a bottom gate 131 formed on an uppersurface of an underlying substrate of structure 5. In certainembodiments, this bottom gate 131 may be a conductive feature alreadypresent on the underlying structure. A first layer or body 41 ofdielectric material is formed over the bottom gate 131, and then a layeror body of initially semi-conductive material has been formed over thatfirst dielectric layer. A central portion of that layer ofsemi-conductive material forms the transistor body or channel 10.Furthermore, suitably processed portions of that initiallysemi-conductive layer that extend beyond the edges of the underlyinglower gate terminal 131 provide the source and drain terminals 11, 12 ofthe device. In other words, the edges of the semi-conductive channel 10(and hence the edge of the source and drain terminals 11, 12) coincidewith the edges of the underlying lower gate terminal 131 such that thereis no overlap between the source on drain terminals 11, 12 and lowergate 131 when viewed from above, so as to minimize any parasiticcapacitors between the source and drain terminals and the gate terminal131. In other words, the projections of the source and drain terminals11, 12 onto the nominal horizontal plane (which generally corresponds tothe plane of the upper surface of the substrate 5 in this figure) do notoverlap the projection of the lower gate terminal 131 onto thathorizontal plane. In this embodiment, the source and drain terminals 11,12 have been extended by the provision of contacts 111 and 121 formedfrom metallic material and which partially overlap each of the sourceand drain terminals 11, 12. A second layer of dielectric material 42 hasbeen formed over the semi-conductive channel 10 and the extended sourceand drain electrodes, and an upper gate terminal 132 has been formed ontop of that second dielectric layer 42. The upper gate 132 is alignedwith both the edges of the semi-conductive channel 10 and the edges ofthe lower gate 131, and has the same projection onto the horizontalplane as the lower gate electrode 131. In other words, the upper andlower gates are aligned and have the same footprint on the horizontalplane. Furthermore, as the source and drain terminals 11, 12 do notoverlap the lower gate terminal 131, they also do not have any overlapwith the upper gate terminal 132. Thus, any parasitic capacitancebetween the upper gate electrode 132 and the source and drain terminalsis also reduced.

It will be appreciated, therefore, that the dual-gate transistorillustrated in FIG. 37 is aligned, in the sense that its lower gateelectrode 131, semi-conductive channel 10, and upper gate electrode 132form an aligned stack, with no overlap between the source and drainterminals and either gate terminal when viewed from a direction normalto the nominal horizontal plane. This alignment may be achieved in avariety of ways. In certain embodiments, this alignment between thesource and drain electrodes in 11 and 12 and the lower gate electrode131 is achieved by forming the source and drain electrodes 11, 12 byirradiating those corresponding portions of the initiallysemi-conductive layer with electromagnetic radiation of the appropriatefrequency from below, i.e. through the substrate 5, such that theradiation affects those irradiated potions but the central portionforming the semi-conductive channel 10 is shielded from that radiationby the lower gate terminal 131 (which of course must be opaque to theradiation of the desired wavelength/frequency).

Referring now to FIG. 38, this shows another dual-gate transistorembodying an aspect of the invention. This transistor has similarstructure that shown in FIG. 37, but here the underlying substrate 5 isa multi-layer structure, with the lower gate electrode 131 again beingprovided on a nominal upper surface of that structure 5. A quantity 100of initially semi-conductive material has been deposited over the lowerdielectric layer 41 and lower gate 131, and again portions of that layerextending laterally beyond the edges of the underlying lower gateelectrode 131 have been suitably processed so as to change theirelectrical properties from semi-conductive to resistive, thus formingthe source and drain terminals 11, 12. In this example a second layer ofdielectric material 42 partially covers the source and drain terminals11, 12 and all of the semi-conductive channel 10, and an upper gateelectrode 132 is formed on top of that second dielectric 42, thissecond, upper gate terminal 132 again being aligned with the lower gateterminal 131 so as to reduce parasitic capacitance.

Referring now to FIG. 39, this illustrates steps in a method suitablefor producing a dual-gate transistor embodying the invention, the methodalso embodying an aspect of the invention. In FIG. 39A, asubstrate/structure 5 is provided, having a nominal upper surface 51 onwhich a lower gate terminal is provided, for example, formed from asuitable metal, then, as show in FIG. 39B, a stack of layers is formedover the lower gate terminal 131, that stack comprising a firstdielectric layer 41 a layer of semi-conductive material 100 (e. g.formed from a metal oxide) and a upper layer of dielectric material 42.This structure is then exposed to electromagnetic radiation of anappropriate frequency (for example, UV radiation) from below. For thistechnique to work then the substrate 5 must of course be at leastpartially transparent to that radiation and the lower gate terminal 131should be opaque. By illuminating the structure from below, the lowergate electrode 131 shields a central portion of the semi-conductivelayer 100 from that radiation, whilst portions of the semi-conductivelayer extending beyond the edges of the lower gate terminal 131 areexposed. In other words, the lower gate 131 is used as a mask and theinterface between the exposed portions of semi-conductive material andthe unexposed central portion are aligned accurately with the edges ofthe lower gate terminal 131. In other words, this technique is able toproduce “self-alignment” between the lower gate terminal and the sourceand drain terminals 11, 12 which are each provided by a respectiveportion of the initially semi-conductive material which has been exposedto the radiation from below, through the substrate. The frequency anddose of radiation is selected as appropriate to result in a change inthe electrical properties of the exposed portions of previouslysemi-conductive material from the semi-conductive to conductive, sincethose exposed portions form the aligned source and drain terminals 11,12 with respect to the lower gate terminal 131 as illustrated in FIG.39C. Then, as illustrated in FIG. 39D, a layer of resist material 9 hasbeen formed over the structure and the resultant structure is againexposed to electromagnetic radiation from below such that the lower gate131 shields a portion 91 of that resist layer 9 from the radiation, butportions 92 of that layer 9 on either side are exposed. The frequencyand dose of this radiation is again selected as appropriate to producethe desired changes in the resist material 9 so as to enable itssubsequent development and processing to form a window W in the resistlayer that window W being aligned with the lower gate 131. It will beappreciate that this radiation using the second reverse exposure stepwill in general be at a different frequency and/or different dose fromthe radiation used in the conversion of portions of the semi-conductivematerial to source and drain terminals 11, 12.

Referring to FIG. 39E, this illustrates a subsequent step where, afterthe window W has been formed in the resist layer 9 (that window Waccurately aligned with the lower gate 131) conducting material 81 hasbeen deposited to form an aligned upper gate terminal 132 inside thewindow W, with remaining portions of the conductive material 81 coveringthe exposed portions 92 of this material on either side of the window W.Then, the structure is processed to remove or lift off the remainingportions 92 of resist material, leaving the structure shown in FIG. 39Fwhich comprises a self-aligned dual-gate transistor. In this example thelower gate 131 has been used as a mask in the formation of both thealigned source and drain terminals 11, 12 and in the formation of thealigned upper gate terminal 132.

In will be appreciated from FIG. 39 and the above description that thematerial used for the formation of the upper electrode 132 in thisexample does not need to be transparent to the radiation used in eitherexposure step.

Referring now to FIG. 40, this shows an alternative technique embodyingthe invention and for producing a self-aligned dual gate transistorembodying the invention. In FIG. 40A a lower gate 131 has again beenprovided on the upper surface of a substrate 5 and a stack of dielectriclayers and a sandwiched layer of initially semi-conductive material hasbeen formed over the lower gate 131. As shown in FIG. 40A (with thearrows) this structure is exposed to suitable electromagnetic radiationfrom below such that the lower gate 131 shields a central portion ofsemi-conductive material, aligned with the lower gate 131, from theradiation and keeps it semi-conductive. However, portions of theinitially semi-conductive material 100 on either side of the shieldedportion are exposed to that radiation, and have their conductiveproperties changed to generally resistive as a result of that radiation.These exposed portions form the source and drain terminals 11, 12 asillustrated in FIG. 40B. A layer of conductive material 1320 is thenformed over the underlying structure, and a layer of resist material 9is formed over the conductive material 1320. The structure is thenexposed to electromagnetic radiation from below such that the lower gate131 acts as a mask for a second time. The material for the conductivelayer 1320 and the radiation used in this second exposure step arechosen such that the radiation is able to pass through the layer ofconductive material 1320 and expose portions of that conductive material1320 on either side of the lower gate 131. However, the lower gate 131acts as a mask such that the radiation in the second exposure step doesnot expose a central portion 91 of the layer of exist material 9. Theresist material is then processed such that just the exposed portions 92are removed leaving the central portion 91 covering a central portion ofthe layer of conductive material 1320 aligned with the lower gate 131, ashown in FIG. 40C. Then, as shown in FIG. 40D, that remaining portion 91of resist material is used as an etch mask to remove portions of thelayer of conductive material 1320 on either side of the etch mask 91,producing an upper gate 132 accurately aligned with the lower gate 131and the source and drain terminals 11, 12 produced form portions of theinitially semi-conductive layer 100.

It will be appreciate that in this embodiment the material used for thetop gate (i.e. the material of the conductive layer 1320) must betransparent to the radiation used in the second exposure step. Again,however, the lower gate 131 has been used as a mask in both theformation of the source and drain terminals 11, 12 aligned to the lowergate and in the formation of the upper gate terminal 132 aligned to thelower gate terminal 131.

Referring now to FIG. 41, this shows steps in yet another methodembodying the invention and for producing a dual gate transistorembodying the invention. As illustrated in FIG. 41A, a lower gate 131 isagain provided on another surface of a substrate 5 over that underlyingstructure there is formed a sequence of layers comprising a firstdielectric layer 41, a layer of initially semi-conductive material 100,a second dielectric layer 42, a layer of conductive material 1320 and alayer of resist material 9. The structure is then exposed to suitableradiation from below such that the lower gate 131 masks central portionsof each of these layers aligned above the lower gate 131 from theradiation. In this example it is, of course, a requirement that, apartfrom the lower gate 131, each of the layers of the stack including thesubstrate 5 should be transparent to the radiation used in this firstexposure. The radiation frequency and dose is chosen such that itsuitably interacts with the exposed portions 92 of the resist layer 9,enabling that resist layer then to be processed so as to remove theexposed portion 92 and leave just the central, shielded portion 91 foruse as an etch mask. Then, that central portion 91 is used as etch maskto remove portions of the layer of conductive material 1320, leavingjust an aligned central portion forming the upper gate 132 (having thesame projection on the horizontal plane as the lower gate 131). Then, asillustrated in FIG. 41C, the structure is again exposed to suitableradiation from below (i.e. through the substrate 5) such that unshieldedportions of the originally semi-conductive layer 100 are converted tosubstantially resistive behavior, becoming the source and drainterminals 11, 12 aligned with the lower gate. A central portion of thepreviously semi-conductive 100 is shielded by lower gate 131, acting asa mask, and becomes the semi-conductive channel or body 10 of thedual-gate transistor.

Referring now to FIG. 42, this illustrates steps in alternative methodembodying the invention and for producing a dual-gate transistorembodying the invention. Here, as shown in FIG. 42A, a lower gate isagain provided on a nominal upper surface of a substrate 5. A layer ofdielectric material 41 is formed over the gate and a layer of initiallysemi-conductive material 100 is formed over that dielectric layer. Alayer of resist material 9 is then formed over the semi-conductivelayer, and the structure is illuminated with suitable electronicradiation from below the substrate such that a central portion 91 of theresist layer is shielded from the radiation by the gate 131 acting as amask, and portions 92 on either side of that central portion are exposedto the radiation. The radiation is arranged to have the desired effecton the resist material such that the resist layer can then be processedso as to remove the exposed portions 92 and leave central portion 91 inplace, aligned with the lower gate 131. Such a structure is show in FIG.42B, and this figure also shows that a layer of conductive material 1320has been formed, part of that layer covering the central portion 91 ofresist material aligned with the lower gate 131 and further portions ofconductive material either side of the resist material 91 coveringportions of the semi-conductive layer 100. Then, the structure isprocessed to lift off that remaining portion 91 of resist material,taking with it the portion of the conductive layer formed on top of it,so leaving just the portions of conductive material 1320 on either sideof the bottom gate (i. e. with their edges aligned with the edges of thebottom gate) and respectively providing the source and drain terminals11, 12. Thus, in this example the source and drain terminals are formednot from portions of the initially semi-conductive layer, but insteadare provided by portions of conductive material self-aligned with thelower gate 131 by using a technique in which the lower gate 131 is againused as a mask. Then, as illustrated in FIG. 42C, a further layer ofdielectric material 42 is formed over the underlying structure, and afurther layer of resist material 9 is formed on top of that seconddielectric layer 42. The structure is then again exposed toelectromagnetic radiation of suitable frequency and dose from below toexpose portions 92 of the resist layer 9 but leave a central portion 91unexposed. It would be appreciate that in this technique the conductivematerial 1320 used for the formation of the source and drain terminals11, 12 must be transparent to the radiation used in the second exposurestep of FIG. 42C. This time, the resist material is processed so as toleave the exposed portions 92 in place, but form a window W aligned withthe lower gate 131 by removing the exposed portion 91. Then a furtherlayer of conductive material 1320 is formed over the structure as shownin FIG. 42D, this conductive material forming a conductive top gate 1320inside the window W, and portions of conductive material also coveringthe remaining portions 92 of resist material on either side. The resistmaterial is then further processed so as to lift off these portions 92,leaving the structure showing FIG. 42E. It will be appreciate that inthis embodiment transparent conductive material is required to make thesource and drain terminals, but in contrast to other embodiments thosesource and drain terminals are not manufactured out of portions of theinitial semi-conductive layer. However, the conductive material used inthe formation of the top gate 132 does not need to be transparent, as itis deposited inside a window W formed in self-alignment with the lowergate 131.

Referring now to FIG. 43, this shows yet another method embodying theinvention and suitable for producing a dual gate transistor alsoembodying the invention. As illustrated in FIG. 43A, a lower gate 131 isprovided on a substrate 5, and a stack of three layers is formed overthat lower gate 131, that stack comprising a first dielectric 41, alayer of semi-conductive material 100 and a second dielectric layer 42.A layer of resist material 9 is formed over the underlying structurewhich is then exposed to suitable radiation from below (through thesubstrate 5) such that the lower gate 131 shields a central portion 91of the resist material from that radiation, leaving portions 92 oneither side exposed, that resist material is then processed suitably toremove the unexposed portion 91, forming a window W in the resist layer9. That window W is self-aligned to the lower gate 131 as the lower gatehas been used as a mask in the formation of that window. Then, as shownin FIG. 43B, the layer of conductive material 1320 has been formed, aportion of that layer inside the window forming the upper gate 132. Thenthe remaining portions and resist material 92 are removed to yield thestructure shown in FIG. 43C. In this embodiment, the conductive materialfor layer 1320 is not transparent to the radiation used in a secondexposure step illustrated in FIG. 43C where the structure is exposed toradiation from above, such that the top gate 132 now acts as a mask,shielding a central portion 10 of the initially semi-conductive layer100 from that radiation from above, but leaving portions on either sideexposed, which have their conductivities increased as an effect of theirradiation becoming generally conductive and forming the source anddrain electrodes 11, 12. Thus, in this example, the non-transparentlower gate 131 is used as a mask in the production of the self-alignedupper gate 132, and then the upper gate 132 is used as a mask in theproduction of the self-aligned source and drain terminals 11, 12.Although FIG. 43C illustrates use of the top gate as a mask in theproduction of the source and drain terminal 11, 12, it will beappreciated that in alternative embodiments the lower gate 131 couldagain be used as a mask for such purposes with the substrate 5 beingilluminated from below rather than above.

Referring now to FIG. 44, it will be appreciated from the abovedescription that certain thin film transistor (TFT) devices embodying anaspect of the invention may employ dual gate electrodes. They may alsoemploy split channel designs. Such devices may also be integrated withresistors, Schottky diodes, or indeed further single gate transistors.In the embodiment illustrated in FIG. 44, a bottom gate 131 has beenformed (or is already provided) on the nominal upper surface of anunderlying structure (or substrate) 5. A layer of dielectric material 41covers the gate 131, and a body of initially semiconductive material 100has been formed on top of that. A second layer of dielectric material 42covers the underlying stack structure, and a top gate 132, aligned withthe bottom gate 131, has been formed by a suitable technique, asdescribed above, in which the bottom gate is used as a mask. In thisexample the top gate material is opaque to the radiation used in thesubsequent exposure step, discussed below. Also in this example, thebody of initially semiconductive material (e.g. comprising a metaloxide) is not uniform, but has a sub-structure comprising a plurality oflayers. This split, or graded, channel feature may also be employed insingle gate transistors, as described above in relation to alternativeembodiments. In the embodiment of FIG. 44 the channel provided by thecentral portion 10 of the body of initially semiconductive material 100comprises three layers 10(1), 10(2), and 10(3). As indicated by thearrows in FIG. 44, self-aligned (to the gates, that is) source and drainterminals 11, 12 are formed from portions of the initiallysemiconductive body 100 by exposing the structure to suitableelectromagnetic radiation from above. The top gate 132 shields (i.e.masks) the central portion 10 from that radiation, leaving theelectrical properties of its three layers unchanged, whereas the effectof exposing the un-masked portions of material 100 to that radiation isto change their electrical characteristics to essentially conductive,rather than semiconductive. In other words, the radiation is arranged topermanently increase the electrical conductivity of the exposedportions. Thus, FIG. 44 illustrates a device stack embodying theinvention and the principle of self-alignment using optical irradiation.

Further details on split channels which may be employed in bottom gate,top gate, or dual gate transistors in embodiments of the invention, areas follows:

The split channels typical consist of two or more layers ofsemiconductor, for example each having tailored conductivity, mobility,carrier concentration, etc. The layers may be produced using differentdeposition conditions, e.g. different oxygen partial pressures duringPVD, different PVD targets, e.g. IGZO of different stoichiometries,and/or doping measures as previously described. The end portions of thelayered semiconductor body (as shown in FIG. 44) are, in theself-alignment approach, irradiated to become conductive; the layers donot become merged or diffused, and their conductivities will bedifferent from each other, but they are all conductive. Additional metalsource/drain contacts may be arranged to make electrical connection tothese end portions (which themselves define the source and drainterminal portions in direct contact with the channel body 10) near tothe device. In a dual gate 3-layer channel device, as shown in FIG. 44,the two interface layers (i.e. 10(1) and 10(3) which are in directcontact with the dielectric layers on either side, i.e. above and belowthe channel portion 10) may be arranged so as to be low in conductivitycompared to the bulk (middle) layer 10(2), so that conduction occurspredominantly at one (or both) clean interface(s) between the threelayers (in other words at the interfaces between 10(1) and 10(2), andbetween 10(2) and 10(3)). This gives improved conduction properties,including higher current, higher mobility, etc. Alternatively, in a dualgate 3-layer channel device, the two interface layers could be high inconductivity compared to the bulk (middle) layer, so that conductionoccurs in two substantially independent channels, each controlled by itsrespective gate. In a single gate 2-layer channel device, the upperinterface layer could be low in conductivity compared to the lower(bulk) layer, so that conduction occurs predominantly at the cleaninterface between the two layers. Benefits as discussed above, and thosebenefits make this split (dual) channel approach relevant to integrationwith Schottky and single gate TFTs (and resistors).

It will be appreciated that certain embodiments are applicable to theprocess of building up a FlexIC on a pre-existing structure, rather thanonto a plain (e.g. glass) carrier. Such pre-existing structures maycomprise arrays of devices, components or features, which may have aconductive surface layer to which the FlexIC devices need to connect.

Certain embodiments comprise at least one dual-gate TFT comprising astack of gate terminal/gate insulator/semiconductor/source-drainterminals/gate insulator/gate terminal. By influencing the electricfield in the semiconductor channel from opposing directions, thecharacteristics of the TFTs may be under greater control. For example,if both gates are electrically connected to each other, the effectiveTFT on-current may be doubled due to the creation of two channels at thetwo interfaces of the semiconductor with the respective gatedielectrics.

When depositing a FlexIC onto an existing structure, e.g. on apart-finished substrate, conductive features or elements on the surfaceof the existing structure may be used as functional elements duringintegration of devices, as described herein, onto the part-finishedsubstrate. This presents an opportunity to generate self-aligned FlexICsincorporating dual gate TFTs, e.g. using conductive features on thesurface of the part-finished substrate as a bottom gate of such a dualgate TFT.

Advantageously, this can allow an effective 2× Ion (i.e. doubling of“on” current) by connecting the two gates, as described above.Alternatively the dual gates may be independently controlled to shiftthreshold voltage (Vt) or create depletion type/like devices.Conventional lithography approaches would mean larger gates at the topto account for overlay, whereas the self-aligned techniques describedherein can produce top gates having the same footprints as, andaccurately aligned with, the bottom gates. In certain embodiments, morecomplexity may be added to the semiconductor stack e.g. using multiplelayers including highly-doped/undoped layers for example. This can bearranged at only at one semiconductor/gate dielectric interface or atboth such interfaces. Similarly to self-aligned top-gate structures, theproperties of an interface layer may be used to selectivelydope/increase the conductivity of areas of semiconductor (optionallyincluding in the channel region). This approach can also be used tocreate resistors. In certain embodiments, the bottom-gate can be used toalign the second (top) gate (or both second gate and second gatedielectric) using rear side exposure, creating either a window (for“lift-off”) or an etch-mask aligned to the first gate. If integratedonto a part-finished substrate that emits radiation or provides someother way of activating the channel, the bottom gate can protect orblock the channel from the LED/light-source/other below. In effect thiswould also mean that the system would “self-align” to the bottom-gate ifthe part-finished substrate below excited or temporarily or permanentlydoped the unprotected channel extending laterally beyond the bottomgate. The device stack could be engineered so that the source and drainelectrodes did not overlap the gate (or either gate).

The same effects may be achieved by UV light irradiation (e.g. from anexcimer laser) through the device stack from above or below to createself-aligned source-drain contacts (i.e. aligned to one, or both, of thegates). From the bottom-side of the substrate one could also align atop-gate to the bottom-gate electrode. The gate-source/drain overlap,rather than the gate-gate overlap, is particularly critical (in terms ofreducing parasitic capacitance, but this approach allows the two gatesto have a similar positional accuracy relative to the SD.

In certain embodiments, use of a doping underlayer (formed e.g. by ALD)may allow doped resistors to be created. Suitable resistors includethose with lateral or vertical orientation, or a combination of both.

In certain embodiments, the underlayer may be formed as part of thebottom-gate process (i.e. it may already be provided on a part-finishedsubstrate).

The dual gate architecture employed in certain embodiments also providesan opportunity to form vertically stacked lateral capacitors integratedinto the stack. This can provides more capacitance per unit area of aFlexIC

In certain embodiments the dual gate TFT stack includes at least 2×ALDlayers with electrodes: BottomGate/Dielectric1/Source-Drain/Dielectric2/Top Gate. The two ALD layersmay be arranged to provide dopants to one or more channel layers.

Referring now to FIG. 45, this shows another circuit module embodyingthe invention and comprising a self-aligned dual gate transistor and aresistor. A layer of initially semiconductive material (e.g. in aninitial “normally off” state) has been formed over the bottom gate andfirst dielectric layer 41. An aligned top gate 132 has been formed,using the bottom gate as a mask, and the top gate has then been used asmask to shield the channel portion 10 from processing (by radiationexposure) to render a portion of the originally semiconductive layerresistive (to form the resistor body 20) and a further portionconductive (to form the drain terminal 12). The resistor body 20 thusdirectly connects to the semiconductor channel, in effect combining thetransistor source and resistor second terminals 11,22

Referring now to FIG. 46, this shows another circuit module embodyingthe invention and comprising a resistor, a top-gate transistor, and aSchottky diode. This circuit module thus integrates three differentdevices, each comprising a respective body of material comprising arespective quantity of the same metal oxide. The module is based on atop gate TFT structure, and has the resistor lifted up so that it isco-planar with, and/or is formed directly or indirectly upon the samedielectric layer as, the diode semiconductor layer. One terminal of thesource/drain terminals of the transistor and one of the Schottkyterminals are provided by a common terminal. That common terminal maythus be described as a source/drain, interconnect, and Schottky diodeelectrode, provided by a single, common body of conductive material. Inthis example, that common terminal/body is formed so as to partiallyoverlap the transistor body and an adjacent portion of a nominal uppersurface of the underlying substate. In this example, the transistor bodymay be formed first, e.g. directly on the substrate, followed byformation of the transistor source/drain terminals, one of which is thecommon electrode/interconnect to the Schottky diode. Then, a layer orother body of dielectric material may be formed over the transistor bodyand source/drain terminals, and then a window or via may be formed downthrough the dielectric layer to expose a portion of an upper surface ofthe common electrode. The quantities of metal oxide material for thediode and resistor bodies may then be formed/deposited/provided, eitherat the same time or in separate processes. If provided in separateprocesses, the process conditions may be adapted such that the quantityof metal oxide material forming the diode body is formed in asemiconducting state (e.g. a “normally off” state), whereas the quantityforming the resistor body is formed in a resistive state (i.e. havinghigher conductivity than the diode body in its non-conducting (i.e. off)state). The diode body at least partly fills the window through thedielectric, contacts the common terminal, and also covers a portion ofan upper surface of the dielectric, that upper surface also directly orindirectly supporting the resistor body. The resistor terminals,transistor gate terminal, and upper terminal of the diode may be formedin at the same time, e.g. by selective deposition, printing, forming andthen patterning a layer of conductive material, or by any other suitabletechnique.

1. A method of manufacturing an electronic circuit (or circuit module)(10000) comprising a first device (1, 3000) and a second device (2,3000), the first device comprising a first terminal (11, 3001), a secondterminal (12, 3002), and a first body (10, 3010) of semiconductivematerial providing a semiconductive path between the first and secondterminals, the second device (2, 3000) comprising a third terminal (21,3001), a fourth terminal (22, 3002), and a second body (20, 3010) ofmaterial providing a resistive or semiconductive current path betweenthe third terminal and the fourth terminal, the method comprising:forming the first body (10, 3010); and forming the second body (20,3010), wherein the first body comprises a first quantity (100, 3100) ofa metal oxide and the second body comprises a second quantity (200,3100) of said metal oxide.
 2. A method in accordance with claim 1,wherein forming the first body comprises forming said first quantity ofsaid metal oxide, and forming the second body comprises forming saidsecond quantity of said metal oxide.
 3. A method in accordance withclaim 2, wherein forming said first quantity comprises forming saidfirst quantity (100) directly or indirectly on a first region (51) of asubstrate (e.g. a flexible substrate), and forming said second quantitycomprises forming said second quantity (200) directly or indirectly on asecond region (52) of the substrate.
 4. A method in accordance with anyone of claim 2 or 3, wherein said forming of said first quantitycomprises forming said first quantity (100) using a technique selectedfrom a list comprising: physical deposition; physical vapour deposition(PVD); chemical deposition; chemical vapour deposition (CVD); atomiclayer deposition (ALD); physical-chemical deposition; evaporation;sputtering; sol-gel techniques; chemical bath deposition; spraypyrolysis; plating techniques; pulsed laser deposition (PLD); solutionprocessing; and spin coating.
 5. A method in accordance with any one ofclaims 2 to 4, wherein said forming of said second quantity comprisesforming said second quantity (200) using a technique selected from alist comprising: physical deposition; physical vapour deposition (PVD);chemical deposition; chemical vapour deposition (CVD); atomic layerdeposition (ALD); physical-chemical deposition; evaporation; sputtering;sol-gel techniques; chemical bath deposition; spray pyrolysis; platingtechniques; pulsed laser deposition (PLD); solution processing; and spincoating.
 6. A method in accordance with any one of claims 2 to 5,wherein forming said first quantity comprises depositing said firstquantity of said metal oxide.
 7. A method in accordance with any one ofclaims 2 to 6, wherein forming said second quantity comprises depositingsaid second quantity of said metal oxide.
 8. A method in accordance withany one of claims 2 to 7, wherein said forming of said first quantity isperformed before said forming of said second quantity.
 9. A method inaccordance with any one of claims 2 to 8, wherein said forming of saidfirst quantity is performed after said forming of said second quantity.10. A method in accordance with any one of claims 2 to 9, wherein, saidforming of said first quantity comprises forming (e.g. by depositing orotherwise forming) a first layer, film, or sheet (1001) of said metaloxide, said first layer, film, or sheet comprising said first quantity(100).
 11. A method in accordance with claim 10, wherein forming thefirst body (10) comprises patterning the first layer, film, or sheet(1001).
 12. A method in accordance with any one of claims 2 to 11,wherein forming of said second quantity comprises forming (e.g. bydepositing or otherwise forming) a second layer, film, or sheet (2001)of said metal oxide, said second layer, film, or sheet comprising saidsecond quantity (200).
 13. A method in accordance with claim 12, whereinforming the second body (2) comprises patterning the second layer, film,or sheet (2001).
 14. A method in accordance with any preceding claim,further comprising doping said first body (10) of material with a firstdopant to decrease or increase an electrical conductivity of said firstbody.
 15. A method in accordance with claim 14, wherein doping saidfirst body of material comprises forming said first quantity (100) on asource (71) of said first dopant.
 16. A method in accordance with claim15, further comprising providing said source (71) of said first dopantdirectly or indirectly on said first region (51) of the substrate.
 17. Amethod in accordance with any one of claims 14 to 16, wherein dopingsaid first body of material comprises forming a source of said firstdopant on said first body of material.
 18. A method in accordance withany preceding claim, further comprising doping said second body (20) ofmaterial with a second dopant to increase or decrease an electricalconductivity of said second body.
 19. A method in accordance with claim18, wherein doping said second body of material comprises forming saidsecond quantity (200) on a source (72) of said second dopant.
 20. Amethod in accordance with claim 19, further comprising providing saidsource (72) of said second dopant directly or indirectly on said secondregion (52) of the substrate.
 21. A method in accordance with any one ofclaims 18 to 20, wherein doping said second body of material comprisesforming a source of said second dopant on said second body of material.22. A method in accordance with any preceding claim, further comprisingprocessing said second quantity (200) of said metal oxide to increase ordecrease an electrical conductivity of the second body.
 23. A method inaccordance with claim 22, wherein processing said second quantitycomprises annealing at least a portion of said second quantity toincrease or decrease its conductivity.
 24. A method in accordance withclaim 22 or claim 23, wherein processing said second quantity comprisesexposing at least a portion of said second quantity to electromagneticradiation.
 25. A method in accordance with claim 24, further comprisingproviding said electromagnetic radiation from a lamp.
 26. A method inaccordance with claim 24, further comprising providing saidelectromagnetic radiation from a laser.
 27. A method in accordance withany one of claims 24 to 26, further comprises shielding at least aportion of the first quantity (100) of said metal oxide from saidelectromagnetic radiation.
 28. A method in accordance with claim 27,wherein said shielding comprises using said gate terminal (13) to shieldsaid at least a portion of the first quantity (100) from saidelectromagnetic radiation.
 29. A method in accordance with any precedingclaim, wherein each of the first and second bodies (10, 20) comprises arespective layer, film, or sheet of said metal oxide, and each saidrespective layer, film, or sheet may have a thickness in the range 1 to200 nm (for example 5 to 50 nm).
 30. A method in accordance with claim29, wherein each said respective layer, film, or sheet has the samethickness.
 31. A method in accordance with claim 29 or claim 30, whereineach said respective layer, film, or sheet is flat (planar).
 32. Amethod in accordance with any preceding claim, further comprisingforming the first and second bodies (10, 20) in a common plane.
 33. Amethod in accordance with any one of claims 1 to 31, further comprisingforming the first body in a first plane and forming the second body in asecond plane, said second plane being parallel to said first plane. 34.A method in accordance with any preceding claim, wherein the second bodyhas a sheet resistance value in the range 25 kOhm/sq to 20 MOhm/sq (e.g.in the range 50 kOhm/sq to 10 MOhm/sq).
 35. A method in accordance withany preceding claim, wherein each of the first and second bodies issubstantially transparent to electromagnetic radiation in the rangevisible to the naked human eye.
 36. A method in accordance with anypreceding claim, further comprising forming the first, second, third,and fourth terminals after forming the first and second bodies.
 37. Amethod in accordance with any one of claims 1 to 35, further comprisesforming the first, second, third, and fourth terminals before formingthe first and second bodies, for example to form bottom contact devices.38. A method in accordance with any preceding claim, wherein said metaloxide is Indium Gallium Zinc Oxide, IGZO.
 39. A method in accordancewith any preceding claim, wherein the first device is a transistor or aSchottky diode, and the second device is a resistor or a Schottky diode.40. A method in accordance with any preceding claim, wherein the circuitfurther comprises a third device (3) having fifth and sixth terminals(31, 32) and a third body (30) of material providing a resistive orsemiconductive current path between said fifth and sixth terminals, themethod comprising forming said third body (30) of material, said thirdbody comprising a third quantity (300) of said metal oxide.
 41. A methodin accordance with claim 39, further comprising doping or processingsaid third body differently from said second body, such that the secondand third bodies exhibit different conductivities at room temperature.42. A method in accordance with claim 40 or claim 41, wherein the thirddevice (3) is a resistor or a Schottky diode.
 43. A method in accordancewith any one of claims 40 to 42, further comprising forming said thirdbody before or after forming at least one of the first and secondbodies.
 44. An electronic circuit (or circuit module) (10000) comprisinga first device (1, 3000) and a second device (2, 3000), the first devicecomprising a first terminal (11, 3001), a second terminal (12, 3002),and a first body (10, 3010) of semiconductive material providing asemiconductive path between the first and second terminals, the seconddevice (2, 3000) comprising a third terminal (21, 3001), a fourthterminal (22, 3002), and a second body (20, 3010)) of material providinga resistive or semiconductive current path between the third terminaland the fourth terminal, wherein said first body (10, 3010) of materialcomprises a metal oxide (e.g. comprises a first quantity (100, 3100) ofsaid metal oxide) and said second body (20, 3010) of material comprisessaid metal oxide (e.g. comprises a second quantity (200, 3100) of saidmetal oxide).
 45. An electronic circuit in accordance with claim 44,wherein the first device is a transistor or a Schottky diode.
 46. Anelectronic circuit in accordance with any one of claim 44 or 45, whereinthe second device is a resistor or a Schottky diode.
 47. An electroniccircuit in accordance with any one of claims 44 to 46, furthercomprising at least one further device having a body comprising saidmetal oxide (e.g. comprising a third quantity of said metal oxide. 48.An electronic circuit in accordance with claim 47, wherein said furtherdevice is a transistor, resistor, or Schottky diode.
 49. An electroniccircuit in accordance with any one of claims 44 to 48, furthercomprising a substrate (e.g. a flexible substrate) arranged to support,directly or indirectly, each of said devices.
 50. A transistor (1)comprising: a source terminal (11), a drain terminal (12), a first body(10) of material providing a controllable semiconductive channel betweenthe source and drain terminals, a first gate terminal (131) arranged onone side of (e.g. under) the first body (10), and a second gate terminal(132) arranged on an opposite side (e.g. above) the first body (10). 51.A transistor in accordance with claim 50, wherein the first gateterminal (131), first body (10), and the second gate terminal (132) arearranged as a stack in a first (i.e. nominally vertical) direction, withthe first body (10) being arranged above the first gate terminal (131)and separated from the first gate terminal (in said first direction) bya first layer or body of dielectric material (41), the second gateterminal (132) being arranged above the first body (10) and separatedfrom the first body (10) (in said first direction) by a second layer orbody of dielectric material (42), and the source and drain terminalsbeing arranged such that there is no overlap between projections ofeither gate terminal with projections of either the source or drainterminals onto a plane normal to said first direction (e.g. a horizontalplane, normal to the vertical direction).
 52. A transistor in accordancewith claim 51, wherein the first and second gate terminals are alignedand arranged to have the same projections as each other onto said plane.53. A transistor in accordance with claim 52, wherein edges of thesource and drain terminals are arranged to coincide with edges of thealigned gate terminals.
 54. A transistor in accordance with any one ofclaims 50 to 53, wherein the first body (10) is provided by a firstportion of a layer of metal oxide material, said first portion beingarranged over said first gate terminal, and said source and drainterminals (11, 12) are provided by respective portions of said layer ofmetal oxide material extending beyond edges of the first gate terminal.55. A transistor in accordance with claim 54, wherein said respectiveportions have higher electrical conductivity than said first body.
 56. Amethod of manufacturing a dual-gate transistor, the method comprising:providing a lower gate terminal supported on a substrate; and using thelower gate terminal as a mask in the formation of an upper gate terminalaligned to the lower gate terminal.
 57. A method in accordance withclaim 56, further comprising: using the lower gate terminal as a mask inthe formation of source and drain terminals aligned to the lower gateterminal.
 58. A method in accordance with claim 56, further comprising:using the upper gate terminal as a mask in the formation of source anddrain terminals aligned to the lower gate terminal.